| Message ID | 20231116131841.1588781-8-imre.deak@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Fix UHBR data, link M/N/TU and PBN values | expand |
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Imre > Deak > Sent: Thursday, November 16, 2023 6:49 PM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH v2 07/11] drm/i915/dp_mst: Calculate the BW > overhead in intel_dp_mst_find_vcpi_slots_for_bpp() > > The next patch will calculate the PBN value directly from the pixel data rate and > the BW allocation overhead, not requiring the data, link M/N and TU values for > this. To prepare for that move the calculation of BW overheads from > intel_dp_mst_compute_m_n() to intel_dp_mst_find_vcpi_slots_for_bpp(). > > While at it store link_bpp in a .4 fixed point format. > > Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Thanks and Regards, Arun R Murthy ------------------- > --- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 27 ++++++++++++++------- > 1 file changed, 18 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c > b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index e5d6b811c22ef..a5ddd1781969d 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -108,15 +108,12 @@ static int intel_dp_mst_bw_overhead(const struct > intel_crtc_state *crtc_state, > > static void intel_dp_mst_compute_m_n(const struct intel_crtc_state > *crtc_state, > const struct intel_connector *connector, > - bool ssc, bool dsc, > + int overhead, > int bpp_x16, > struct intel_link_m_n *m_n) > { > const struct drm_display_mode *adjusted_mode = > &crtc_state->hw.adjusted_mode; > - int overhead = intel_dp_mst_bw_overhead(crtc_state, > - connector, > - ssc, dsc, bpp_x16); > > intel_link_compute_m_n(bpp_x16, crtc_state->lane_count, > adjusted_mode->crtc_clock, > @@ -171,7 +168,9 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct > intel_encoder *encoder, > > for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) { > struct intel_link_m_n remote_m_n; > - int link_bpp; > + int local_bw_overhead; > + int remote_bw_overhead; > + int link_bpp_x16; > > drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp); > > @@ -179,12 +178,22 @@ static int > intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, > if (ret) > continue; > > - link_bpp = dsc ? bpp : > - intel_dp_output_bpp(crtc_state->output_format, bpp); > + link_bpp_x16 = to_bpp_x16(dsc ? bpp : > + intel_dp_output_bpp(crtc_state- > >output_format, bpp)); > > - intel_dp_mst_compute_m_n(crtc_state, connector, false, dsc, > to_bpp_x16(link_bpp), > + local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, > connector, > + false, dsc, > link_bpp_x16); > + remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, > connector, > + true, dsc, > link_bpp_x16); > + > + intel_dp_mst_compute_m_n(crtc_state, connector, > + local_bw_overhead, > + link_bpp_x16, > &crtc_state->dp_m_n); > - intel_dp_mst_compute_m_n(crtc_state, connector, true, dsc, > to_bpp_x16(link_bpp), > + > + intel_dp_mst_compute_m_n(crtc_state, connector, > + remote_bw_overhead, > + link_bpp_x16, > &remote_m_n); > > /* > -- > 2.39.2
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index e5d6b811c22ef..a5ddd1781969d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -108,15 +108,12 @@ static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state, static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state, const struct intel_connector *connector, - bool ssc, bool dsc, + int overhead, int bpp_x16, struct intel_link_m_n *m_n) { const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; - int overhead = intel_dp_mst_bw_overhead(crtc_state, - connector, - ssc, dsc, bpp_x16); intel_link_compute_m_n(bpp_x16, crtc_state->lane_count, adjusted_mode->crtc_clock, @@ -171,7 +168,9 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) { struct intel_link_m_n remote_m_n; - int link_bpp; + int local_bw_overhead; + int remote_bw_overhead; + int link_bpp_x16; drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp); @@ -179,12 +178,22 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, if (ret) continue; - link_bpp = dsc ? bpp : - intel_dp_output_bpp(crtc_state->output_format, bpp); + link_bpp_x16 = to_bpp_x16(dsc ? bpp : + intel_dp_output_bpp(crtc_state->output_format, bpp)); - intel_dp_mst_compute_m_n(crtc_state, connector, false, dsc, to_bpp_x16(link_bpp), + local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, connector, + false, dsc, link_bpp_x16); + remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, connector, + true, dsc, link_bpp_x16); + + intel_dp_mst_compute_m_n(crtc_state, connector, + local_bw_overhead, + link_bpp_x16, &crtc_state->dp_m_n); - intel_dp_mst_compute_m_n(crtc_state, connector, true, dsc, to_bpp_x16(link_bpp), + + intel_dp_mst_compute_m_n(crtc_state, connector, + remote_bw_overhead, + link_bpp_x16, &remote_m_n); /*
The next patch will calculate the PBN value directly from the pixel data rate and the BW allocation overhead, not requiring the data, link M/N and TU values for this. To prepare for that move the calculation of BW overheads from intel_dp_mst_compute_m_n() to intel_dp_mst_find_vcpi_slots_for_bpp(). While at it store link_bpp in a .4 fixed point format. Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 27 ++++++++++++++------- 1 file changed, 18 insertions(+), 9 deletions(-)