From patchwork Mon Dec 4 11:58:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mika Kahola X-Patchwork-Id: 13478252 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F3FC7C10DC1 for ; Mon, 4 Dec 2023 12:05:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A09AC10E19D; Mon, 4 Dec 2023 12:05:51 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id BC4EF10E39D for ; Mon, 4 Dec 2023 12:05:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701691533; x=1733227533; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2WJQ1MtcjMupOYL4iwxFTGQ0ZGHNd/7VML3wW6qlZyc=; b=Lo7czKi7fKqZs+ORODFjqsdocjMQ1RXarFbcJvPDOQT3sCUyoXKxUnV5 CGMLVQw0UtMhIqHcsxd2aJ/UXjCmkgS1P1i9GSNNAJp4TntkyVPgG+X7c Oo4cyOBqrrLt56xwQVnxrlcKOCTEcknG6BUUc9CzgGPfnrgCqf05ukDyA n9gmzjba03AAxDiClaz/3TzCo8pS8Ou6k7PGD1wL6yRnI9G+Fry1zeAy/ u2TJtjXNPiOKiJ3yd6RSMqBumzkNOlWKGoWLiWtPy7ytuLwNDipQYj0J8 xV0J+GT4RdQt9IG0R7R/mw1MAJvl1BcI6gSQFAMILzqI1B2Zowd5Yq9w8 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10913"; a="460216917" X-IronPort-AV: E=Sophos;i="6.04,249,1695711600"; d="scan'208";a="460216917" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2023 04:05:21 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10913"; a="836565370" X-IronPort-AV: E=Sophos;i="6.04,249,1695711600"; d="scan'208";a="836565370" Received: from sorvi2.fi.intel.com ([10.237.72.194]) by fmsmga008.fm.intel.com with ESMTP; 04 Dec 2023 04:05:20 -0800 From: Mika Kahola To: intel-gfx@lists.freedesktop.org Date: Mon, 4 Dec 2023 13:58:54 +0200 Message-Id: <20231204115856.176240-2-mika.kahola@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231204115856.176240-1-mika.kahola@intel.com> References: <20231204115856.176240-1-mika.kahola@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/3] drm/i915/display: Move C20 HW readout X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Moving intel_c20pll_readout_hw_state() for better place to better suit for upcoming changes. Signed-off-by: Mika Kahola --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 116 +++++++++---------- 1 file changed, 58 insertions(+), 58 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 5fbec5784b83..2e6412fc2258 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2123,64 +2123,6 @@ static bool intel_c20_use_mplla(u32 clock) return false; } -static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder, - struct intel_c20pll_state *pll_state) -{ - struct drm_i915_private *i915 = to_i915(encoder->base.dev); - bool cntx; - intel_wakeref_t wakeref; - int i; - - wakeref = intel_cx0_phy_transaction_begin(encoder); - - /* 1. Read current context selection */ - cntx = intel_cx0_read(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE; - - /* Read Tx configuration */ - for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { - if (cntx) - pll_state->tx[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, - PHY_C20_B_TX_CNTX_CFG(i)); - else - pll_state->tx[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, - PHY_C20_A_TX_CNTX_CFG(i)); - } - - /* Read common configuration */ - for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) { - if (cntx) - pll_state->cmn[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, - PHY_C20_B_CMN_CNTX_CFG(i)); - else - pll_state->cmn[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, - PHY_C20_A_CMN_CNTX_CFG(i)); - } - - if (pll_state->tx[0] & C20_PHY_USE_MPLLB) { - /* MPLLB configuration */ - for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) { - if (cntx) - pll_state->mpllb[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, - PHY_C20_B_MPLLB_CNTX_CFG(i)); - else - pll_state->mpllb[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, - PHY_C20_A_MPLLB_CNTX_CFG(i)); - } - } else { - /* MPLLA configuration */ - for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) { - if (cntx) - pll_state->mplla[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, - PHY_C20_B_MPLLA_CNTX_CFG(i)); - else - pll_state->mplla[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, - PHY_C20_A_MPLLA_CNTX_CFG(i)); - } - } - - intel_cx0_phy_transaction_end(encoder, wakeref); -} - void intel_c20pll_dump_hw_state(struct drm_i915_private *i915, const struct intel_c20pll_state *hw_state) { @@ -2503,6 +2445,64 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder, XELPDP_SSC_ENABLE_PLLB, val); } +static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder, + struct intel_c20pll_state *pll_state) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + bool cntx; + intel_wakeref_t wakeref; + int i; + + wakeref = intel_cx0_phy_transaction_begin(encoder); + + /* 1. Read current context selection */ + cntx = intel_cx0_read(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE; + + /* Read Tx configuration */ + for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { + if (cntx) + pll_state->tx[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, + PHY_C20_B_TX_CNTX_CFG(i)); + else + pll_state->tx[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, + PHY_C20_A_TX_CNTX_CFG(i)); + } + + /* Read common configuration */ + for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) { + if (cntx) + pll_state->cmn[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, + PHY_C20_B_CMN_CNTX_CFG(i)); + else + pll_state->cmn[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, + PHY_C20_A_CMN_CNTX_CFG(i)); + } + + if (pll_state->tx[0] & C20_PHY_USE_MPLLB) { + /* MPLLB configuration */ + for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) { + if (cntx) + pll_state->mpllb[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, + PHY_C20_B_MPLLB_CNTX_CFG(i)); + else + pll_state->mpllb[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, + PHY_C20_A_MPLLB_CNTX_CFG(i)); + } + } else { + /* MPLLA configuration */ + for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) { + if (cntx) + pll_state->mplla[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, + PHY_C20_B_MPLLA_CNTX_CFG(i)); + else + pll_state->mplla[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0, + PHY_C20_A_MPLLA_CNTX_CFG(i)); + } + } + + intel_cx0_phy_transaction_end(encoder, wakeref); +} + static u32 intel_cx0_get_powerdown_update(u8 lane_mask) { u32 val = 0;