| Message ID | 20231219123246.832245-1-mika.kahola@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/display: Skip C10 state verification in case of fastset | expand |
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Mika > Kahola > Sent: Tuesday, December 19, 2023 4:33 AM > To: intel-gfx@lists.freedesktop.org > Subject: [PATCH] drm/i915/display: Skip C10 state verification in case of fastset > > PLL's are not programmed in case of fastset so the state > verfication compares bios programmed PLL values against > sw PLL values. To overcome this limitation, we can skip > the state verification for C10 in fastset case as the > driver is not writing PLL values. > LGTM, Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > Signed-off-by: Mika Kahola <mika.kahola@intel.com> > --- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > index 884a1da36089..3ef54eaca9e4 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > @@ -3016,6 +3016,9 @@ static void intel_c10pll_state_verify(const struct > intel_crtc_state *state, > const struct intel_c10pll_state *mpllb_sw_state = &state- > >cx0pll_state.c10; > int i; > > + if (intel_crtc_needs_fastset(state)) > + return; > + > for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) { > u8 expected = mpllb_sw_state->pll[i]; > > -- > 2.34.1
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 884a1da36089..3ef54eaca9e4 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -3016,6 +3016,9 @@ static void intel_c10pll_state_verify(const struct intel_crtc_state *state, const struct intel_c10pll_state *mpllb_sw_state = &state->cx0pll_state.c10; int i; + if (intel_crtc_needs_fastset(state)) + return; + for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) { u8 expected = mpllb_sw_state->pll[i];
PLL's are not programmed in case of fastset so the state verfication compares bios programmed PLL values against sw PLL values. To overcome this limitation, we can skip the state verification for C10 in fastset case as the driver is not writing PLL values. Signed-off-by: Mika Kahola <mika.kahola@intel.com> --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 3 +++ 1 file changed, 3 insertions(+)