@@ -5100,7 +5100,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
}
if (intel_phy_is_tc(dev_priv, phy)) {
- bool is_legacy =
+ bool is_legacy = HAS_LEGACY_TC(dev_priv) &&
!intel_bios_encoder_supports_typec_usb(devdata) &&
!intel_bios_encoder_supports_tbt(devdata);
@@ -1854,17 +1854,9 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
return false;
}
-bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
+static bool intel_phy_is_legacy_tc(struct drm_i915_private *dev_priv, enum phy phy)
{
- /*
- * DG2's "TC1", although TC-capable output, doesn't share the same flow
- * as other platforms on the display engine side and rather rely on the
- * SNPS PHY, that is programmed separately
- */
- if (IS_DG2(dev_priv))
- return false;
-
- if (DISPLAY_VER(dev_priv) >= 13)
+ if (DISPLAY_VER(dev_priv) == 13)
return phy >= PHY_F && phy <= PHY_I;
else if (IS_TIGERLAKE(dev_priv))
return phy >= PHY_D && phy <= PHY_I;
@@ -1874,6 +1866,23 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
return false;
}
+static bool intel_phy_is_vbt_tc(struct drm_i915_private *dev_priv, enum phy phy)
+{
+ const struct intel_bios_encoder_data *data =
+ intel_bios_encoder_phy_data_lookup(dev_priv, phy);
+
+ return intel_bios_encoder_supports_typec_usb(data) &&
+ intel_bios_encoder_supports_tbt(data);
+}
+
+bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
+{
+ if (!HAS_LEGACY_TC(dev_priv))
+ return intel_phy_is_vbt_tc(dev_priv, phy);
+ else
+ return intel_phy_is_legacy_tc(dev_priv, phy);
+}
+
bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy)
{
/*
@@ -58,6 +58,7 @@ struct drm_printer;
#define HAS_IPS(i915) (IS_HASWELL_ULT(i915) || IS_BROADWELL(i915))
#define HAS_LRR(i915) (DISPLAY_VER(i915) >= 12)
#define HAS_LSPCON(i915) (IS_DISPLAY_VER(i915, 9, 10))
+#define HAS_LEGACY_TC(i915) (IS_DISPLAY_VER(i915, 11, 13) && !IS_DGFX(i915))
#define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
#define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12)
#define HAS_OVERLAY(i915) (DISPLAY_INFO(i915)->has_overlay)
Starting MTL and DG2 if a phy is not marked as USB-typeC or TBT capable by vbt we should not consider it as a Legacy type-c phy. The concept of Legacy-tc existed in platforms from Icelake to Alder lake where an external FIA can be routed to one of the phy's thus making the phy tc capable without being marked in the vbt. Discrete cards have native ports and client products post MTL have a 1:1 mapping with type-C subsystem which is advertised by the bios. So rely on the vbt info regarding type-c capability. Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 29 ++++++++++++------- .../drm/i915/display/intel_display_device.h | 1 + 3 files changed, 21 insertions(+), 11 deletions(-)