From patchwork Thu Dec 21 17:08:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13502412 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 56E9DC46CCD for ; Thu, 21 Dec 2023 17:09:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B220910E6DE; Thu, 21 Dec 2023 17:09:58 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 555AB10E375; Thu, 21 Dec 2023 17:09:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703178597; x=1734714597; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DC5wUxyUZuDXqHwb6BLbsrDJRiz4sPLtJ5GVpqfvxUU=; b=IfzJJcI8XBlTYDP6+8l0EbhR0uXApWiqpgT2UeoxYs/jnAAqpRyml3KQ iCK6O9G6q7IN0HSw38ScpU0b5siB9KLhN6DOKVZOhmBI2rHnivxHmCIUn QqOOxLLJcCdwtXp4w40JB7H+pVAk3U3GKcd8lxcqY2sf98NCwpIcl4hWY +iw9YysG3kDqJhXeZTqzxsCnBk1Rk20ufYkwkEy/5fvudGB9woegNFgF9 pn8HH6X4h8VllJhSlRabZKhRanOTdkHYVAMmFQzSkssG2WpaetcLhB0MC KSXVi6RXxWSAfGE6rt+UyHSV9rv1T1YlO/wpv4sIu1SMeZbOHP7o4DKwK w==; X-IronPort-AV: E=McAfee;i="6600,9927,10931"; a="482188830" X-IronPort-AV: E=Sophos;i="6.04,293,1695711600"; d="scan'208";a="482188830" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Dec 2023 09:08:58 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10931"; a="770008528" X-IronPort-AV: E=Sophos;i="6.04,293,1695711600"; d="scan'208";a="770008528" Received: from dgiardin-mobl.ger.corp.intel.com (HELO intel.com) ([10.249.35.73]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Dec 2023 09:08:56 -0800 From: Andi Shyti To: intel-gfx , dri-devel Subject: [PATCH 3/3] drm/i915/gt: Disable HW load balancing for CCS Date: Thu, 21 Dec 2023 18:08:24 +0100 Message-ID: <20231221170825.356970-4-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231221170825.356970-1-andi.shyti@linux.intel.com> References: <20231221170825.356970-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Chris Wilson Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The hardware is not able to dynamically balance the load between CCS engines. Wa_16016805146 suggests disabling it for all platforms. Signed-off-by: Andi Shyti Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Niranjana Vishwanathapura Cc: Tejas Upadhyay --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 3e558d6d5e89..edaa446abd91 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1478,6 +1478,7 @@ #define GEN12_RCU_MODE _MMIO(0x14800) #define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0) +#define XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1) #define CHV_FUSE_GT _MMIO(VLV_GUNIT_BASE + 0x2168) #define CHV_FGT_DISABLE_SS0 (1 << 10) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 3eacbc50caf8..a7718f7d2925 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2978,6 +2978,12 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); } + + /* + * Wa_16016805146: disable the CCS load balancing + * indiscriminately for all the platforms + */ + wa_masked_en(wal, GEN12_RCU_MODE, XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE); } static void