| Message ID | 20240104032150.118954-2-gustavo.sousa@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Update bxt_sanitize_cdclk() for Xe2_LPD | expand |
On Thu, Jan 04, 2024 at 12:21:47AM -0300, Gustavo Sousa wrote: > With Xe2_LPD, there were changes to the way CDCLK_CTL must be > programmed. Those were reflected on _bxt_set_cdclk() with commit > 3d3696c0fed1 ("drm/i915/lnl: Start using CDCLK through PLL"), but > bxt_sanitize_cdclk() was left out. > > This was causing some issues when loading the driver with a pre-existing > active display configuration: the driver would mistakenly take the > current value of CDCLK_CTL as wrong and the sanitization would be > triggered. > > In a scenario where the display was already configured with a high > CDCLKC and had plane(s) enabled, FIFO underrun errors were reported, > because the current sanitization code selects the minimum possible > CDCLK. > > Fix that by updating bxt_sanitize_cdclk() to match the changes made in > _bxt_set_cdclk(). Ideally, we would have a common function to derive the > value for CDCLK_CTL, but that can be done in a future change. > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c > index c5fecde7afa8..0012e3171f3f 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -2071,7 +2071,10 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) > if (vco != dev_priv->display.cdclk.hw.vco) > goto sanitize; > > - expected = skl_cdclk_decimal(cdclk); > + if (DISPLAY_VER(dev_priv) >= 20) > + expected = MDCLK_SOURCE_SEL_CDCLK_PLL; > + else > + expected = skl_cdclk_decimal(cdclk); > > /* Figure out what CD2X divider we should be using for this cdclk */ > if (HAS_CDCLK_SQUASH(dev_priv)) > -- > 2.43.0 >
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index c5fecde7afa8..0012e3171f3f 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2071,7 +2071,10 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) if (vco != dev_priv->display.cdclk.hw.vco) goto sanitize; - expected = skl_cdclk_decimal(cdclk); + if (DISPLAY_VER(dev_priv) >= 20) + expected = MDCLK_SOURCE_SEL_CDCLK_PLL; + else + expected = skl_cdclk_decimal(cdclk); /* Figure out what CD2X divider we should be using for this cdclk */ if (HAS_CDCLK_SQUASH(dev_priv))
With Xe2_LPD, there were changes to the way CDCLK_CTL must be programmed. Those were reflected on _bxt_set_cdclk() with commit 3d3696c0fed1 ("drm/i915/lnl: Start using CDCLK through PLL"), but bxt_sanitize_cdclk() was left out. This was causing some issues when loading the driver with a pre-existing active display configuration: the driver would mistakenly take the current value of CDCLK_CTL as wrong and the sanitization would be triggered. In a scenario where the display was already configured with a high CDCLKC and had plane(s) enabled, FIFO underrun errors were reported, because the current sanitization code selects the minimum possible CDCLK. Fix that by updating bxt_sanitize_cdclk() to match the changes made in _bxt_set_cdclk(). Ideally, we would have a common function to derive the value for CDCLK_CTL, but that can be done in a future change. Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> --- drivers/gpu/drm/i915/display/intel_cdclk.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)