| Message ID | 20240212173623.1464540-5-mitulkumar.ajitkumar.golani@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Enable Adaptive Sync SDP Support for DP | expand |
On 2/12/2024 11:06 PM, Mitul Golani wrote: > Add necessary functions definitions to enable > and compute AS SDP data. The new `intel_dp_compute_as_sdp` > function computes AS SDP values based on the display > configuration, ensuring proper handling of Variable Refresh > Rate (VRR). > > --v2: > - Add DP_SDP_ADAPTIVE_SYNC to infoframe_type_to_idx().[Ankit] > - separate patch for intel_read/write_dp_sdp [Ankit]. > - _HSW_VIDEO_DIP_ASYNC_DATA_A should be from ADL onward [Ankit] > - To fix indentation [Ankit] > > --v3: > - Add VIDEO_DIP_ENABLE_AS_HSW flag to intel_dp_set_infoframes. > > --v4: > - Add HAS_VRR check before write as sdp. > > --v5: > - Add missed HAS_VRR check before read as sdp. > > Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 3 +++ > drivers/gpu/drm/i915/display/intel_dp.c | 23 +++++++++++++++++++++++ > 2 files changed, 26 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index bea441590204..47dfe727e98a 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -3972,6 +3972,9 @@ static void intel_ddi_get_config(struct intel_encoder *encoder, > intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); > intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); > > + if ((DISPLAY_VER(dev_priv) >= 13) && HAS_VRR(dev_priv)) > + intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC); > + > intel_audio_codec_get_config(encoder, pipe_config); > } > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 6e9180ce069a..7ecbe9f48847 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -2615,6 +2615,25 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc > vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED; > } > > +static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp, > + struct intel_crtc_state *crtc_state, > + const struct drm_connector_state *conn_state) > +{ > + struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp; > + struct intel_connector *connector = intel_dp->attached_connector; > + const struct drm_display_mode *adjusted_mode = > + &crtc_state->hw.adjusted_mode; > + int vrefresh = drm_mode_vrefresh(adjusted_mode); > + > + if (!intel_vrr_is_in_range(connector, vrefresh)) > + return; > + > + crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC); > + as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC; > + as_sdp->length = 0x9; > + as_sdp->vtotal = adjusted_mode->vtotal; > +} > + > static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, > struct intel_crtc_state *crtc_state, > const struct drm_connector_state *conn_state) > @@ -2940,6 +2959,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, > g4x_dp_set_clock(encoder, pipe_config); > > intel_vrr_compute_config(pipe_config, conn_state); > + intel_dp_compute_as_sdp(intel_dp, pipe_config, conn_state); > intel_psr_compute_config(intel_dp, pipe_config, conn_state); > intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16); > intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state); > @@ -4325,6 +4345,9 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder, > > intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC); > > + if ((DISPLAY_VER(dev_priv) >= 13) && HAS_VRR(dev_priv)) > + intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC); I think we need to check whether adaptive sync SDP is supported by the sink or not from 2214h. It would be good to have functions to get AS SDP capability for both sink and source, which can be used before read and write dp_sdps Regards, Ankit > + > intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA); > } >
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index bea441590204..47dfe727e98a 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3972,6 +3972,9 @@ static void intel_ddi_get_config(struct intel_encoder *encoder, intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); + if ((DISPLAY_VER(dev_priv) >= 13) && HAS_VRR(dev_priv)) + intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC); + intel_audio_codec_get_config(encoder, pipe_config); } diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 6e9180ce069a..7ecbe9f48847 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2615,6 +2615,25 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED; } +static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp, + struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state) +{ + struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp; + struct intel_connector *connector = intel_dp->attached_connector; + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + int vrefresh = drm_mode_vrefresh(adjusted_mode); + + if (!intel_vrr_is_in_range(connector, vrefresh)) + return; + + crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC); + as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC; + as_sdp->length = 0x9; + as_sdp->vtotal = adjusted_mode->vtotal; +} + static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) @@ -2940,6 +2959,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, g4x_dp_set_clock(encoder, pipe_config); intel_vrr_compute_config(pipe_config, conn_state); + intel_dp_compute_as_sdp(intel_dp, pipe_config, conn_state); intel_psr_compute_config(intel_dp, pipe_config, conn_state); intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16); intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state); @@ -4325,6 +4345,9 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder, intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC); + if ((DISPLAY_VER(dev_priv) >= 13) && HAS_VRR(dev_priv)) + intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC); + intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA); }
Add necessary functions definitions to enable and compute AS SDP data. The new `intel_dp_compute_as_sdp` function computes AS SDP values based on the display configuration, ensuring proper handling of Variable Refresh Rate (VRR). --v2: - Add DP_SDP_ADAPTIVE_SYNC to infoframe_type_to_idx().[Ankit] - separate patch for intel_read/write_dp_sdp [Ankit]. - _HSW_VIDEO_DIP_ASYNC_DATA_A should be from ADL onward [Ankit] - To fix indentation [Ankit] --v3: - Add VIDEO_DIP_ENABLE_AS_HSW flag to intel_dp_set_infoframes. --v4: - Add HAS_VRR check before write as sdp. --v5: - Add missed HAS_VRR check before read as sdp. Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 3 +++ drivers/gpu/drm/i915/display/intel_dp.c | 23 +++++++++++++++++++++++ 2 files changed, 26 insertions(+)