| Message ID | 20240214070713.1028297-1-ravi.kumar.vodapalli@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/display: update pll values in sync with Bspec for MTL | expand |
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ravi Kumar Vodapalli > Sent: Wednesday, February 14, 2024 9:07 AM > To: intel-gfx@lists.freedesktop.org > Cc: Roper, Matthew D <matthew.d.roper@intel.com>; Vivekanandan, Balasubramani <balasubramani.vivekanandan@intel.com>; > De Marchi, Lucas <lucas.demarchi@intel.com>; Taylor, Clinton A <clinton.a.taylor@intel.com>; Kalvala, Haridhar > <haridhar.kalvala@intel.com>; Sripada, Radhakrishna <radhakrishna.sripada@intel.com>; Atwood, Matthew S > <matthew.s.atwood@intel.com>; Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@intel.com> > Subject: [PATCH] drm/i915/display: update pll values in sync with Bspec for MTL > > DP/eDP and HDMI C20 PHY PLL values were updated for MTL platform > Looks valid update to the pll tables. Reviewed-by: Mika Kahola <mika.kahola@intel.com> > Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com> > --- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 32 ++++++++++---------- > 1 file changed, 16 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > index 288a00e083c8..64e0f820a789 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > @@ -848,10 +848,10 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr3 = { static const struct intel_c20pll_state > mtl_c20_dp_uhbr10 = { > .clock = 1000000, /* 10 Gbps */ > .tx = { 0xbe21, /* tx cfg0 */ > - 0x4800, /* tx cfg1 */ > + 0xe800, /* tx cfg1 */ > 0x0000, /* tx cfg2 */ > }, > - .cmn = {0x0500, /* cmn cfg0*/ > + .cmn = {0x0700, /* cmn cfg0*/ > 0x0005, /* cmn cfg1 */ > 0x0000, /* cmn cfg2 */ > 0x0000, /* cmn cfg3 */ > @@ -1641,7 +1641,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_594 = { static const struct intel_c20pll_state > mtl_c20_hdmi_300 = { > .clock = 3000000, > .tx = { 0xbe98, /* tx cfg0 */ > - 0x9800, /* tx cfg1 */ > + 0x8800, /* tx cfg1 */ > 0x0000, /* tx cfg2 */ > }, > .cmn = { 0x0500, /* cmn cfg0*/ > @@ -1649,8 +1649,8 @@ static const struct intel_c20pll_state mtl_c20_hdmi_300 = { > 0x0000, /* cmn cfg2 */ > 0x0000, /* cmn cfg3 */ > }, > - .mpllb = { 0x209c, /* mpllb cfg0 */ > - 0x7d10, /* mpllb cfg1 */ > + .mpllb = { 0x309c, /* mpllb cfg0 */ > + 0x2110, /* mpllb cfg1 */ > 0xca06, /* mpllb cfg2 */ > 0xbe40, /* mpllb cfg3 */ > 0x0000, /* mpllb cfg4 */ > @@ -1666,7 +1666,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_300 = { static const struct intel_c20pll_state > mtl_c20_hdmi_600 = { > .clock = 6000000, > .tx = { 0xbe98, /* tx cfg0 */ > - 0x9800, /* tx cfg1 */ > + 0x8800, /* tx cfg1 */ > 0x0000, /* tx cfg2 */ > }, > .cmn = { 0x0500, /* cmn cfg0*/ > @@ -1674,8 +1674,8 @@ static const struct intel_c20pll_state mtl_c20_hdmi_600 = { > 0x0000, /* cmn cfg2 */ > 0x0000, /* cmn cfg3 */ > }, > - .mpllb = { 0x009c, /* mpllb cfg0 */ > - 0x7d08, /* mpllb cfg1 */ > + .mpllb = { 0x109c, /* mpllb cfg0 */ > + 0x2108, /* mpllb cfg1 */ > 0xca06, /* mpllb cfg2 */ > 0xbe40, /* mpllb cfg3 */ > 0x0000, /* mpllb cfg4 */ > @@ -1691,7 +1691,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_600 = { static const struct intel_c20pll_state > mtl_c20_hdmi_800 = { > .clock = 8000000, > .tx = { 0xbe98, /* tx cfg0 */ > - 0x9800, /* tx cfg1 */ > + 0x8800, /* tx cfg1 */ > 0x0000, /* tx cfg2 */ > }, > .cmn = { 0x0500, /* cmn cfg0*/ > @@ -1699,8 +1699,8 @@ static const struct intel_c20pll_state mtl_c20_hdmi_800 = { > 0x0000, /* cmn cfg2 */ > 0x0000, /* cmn cfg3 */ > }, > - .mpllb = { 0x00d0, /* mpllb cfg0 */ > - 0x7d08, /* mpllb cfg1 */ > + .mpllb = { 0x10d0, /* mpllb cfg0 */ > + 0x2108, /* mpllb cfg1 */ > 0x4a06, /* mpllb cfg2 */ > 0xbe40, /* mpllb cfg3 */ > 0x0000, /* mpllb cfg4 */ > @@ -1716,7 +1716,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_800 = { static const struct intel_c20pll_state > mtl_c20_hdmi_1000 = { > .clock = 10000000, > .tx = { 0xbe98, /* tx cfg0 */ > - 0x9800, /* tx cfg1 */ > + 0x8800, /* tx cfg1 */ > 0x0000, /* tx cfg2 */ > }, > .cmn = { 0x0500, /* cmn cfg0*/ > @@ -1725,7 +1725,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_1000 = { > 0x0000, /* cmn cfg3 */ > }, > .mpllb = { 0x1104, /* mpllb cfg0 */ > - 0x7d08, /* mpllb cfg1 */ > + 0x2108, /* mpllb cfg1 */ > 0x0a06, /* mpllb cfg2 */ > 0xbe40, /* mpllb cfg3 */ > 0x0000, /* mpllb cfg4 */ > @@ -1741,7 +1741,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_1000 = { static const struct intel_c20pll_state > mtl_c20_hdmi_1200 = { > .clock = 12000000, > .tx = { 0xbe98, /* tx cfg0 */ > - 0x9800, /* tx cfg1 */ > + 0x8800, /* tx cfg1 */ > 0x0000, /* tx cfg2 */ > }, > .cmn = { 0x0500, /* cmn cfg0*/ > @@ -1749,8 +1749,8 @@ static const struct intel_c20pll_state mtl_c20_hdmi_1200 = { > 0x0000, /* cmn cfg2 */ > 0x0000, /* cmn cfg3 */ > }, > - .mpllb = { 0x0138, /* mpllb cfg0 */ > - 0x7d08, /* mpllb cfg1 */ > + .mpllb = { 0x1138, /* mpllb cfg0 */ > + 0x2108, /* mpllb cfg1 */ > 0x5486, /* mpllb cfg2 */ > 0xfe40, /* mpllb cfg3 */ > 0x0000, /* mpllb cfg4 */ > -- > 2.25.1
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 288a00e083c8..64e0f820a789 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -848,10 +848,10 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr3 = { static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = { .clock = 1000000, /* 10 Gbps */ .tx = { 0xbe21, /* tx cfg0 */ - 0x4800, /* tx cfg1 */ + 0xe800, /* tx cfg1 */ 0x0000, /* tx cfg2 */ }, - .cmn = {0x0500, /* cmn cfg0*/ + .cmn = {0x0700, /* cmn cfg0*/ 0x0005, /* cmn cfg1 */ 0x0000, /* cmn cfg2 */ 0x0000, /* cmn cfg3 */ @@ -1641,7 +1641,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_594 = { static const struct intel_c20pll_state mtl_c20_hdmi_300 = { .clock = 3000000, .tx = { 0xbe98, /* tx cfg0 */ - 0x9800, /* tx cfg1 */ + 0x8800, /* tx cfg1 */ 0x0000, /* tx cfg2 */ }, .cmn = { 0x0500, /* cmn cfg0*/ @@ -1649,8 +1649,8 @@ static const struct intel_c20pll_state mtl_c20_hdmi_300 = { 0x0000, /* cmn cfg2 */ 0x0000, /* cmn cfg3 */ }, - .mpllb = { 0x209c, /* mpllb cfg0 */ - 0x7d10, /* mpllb cfg1 */ + .mpllb = { 0x309c, /* mpllb cfg0 */ + 0x2110, /* mpllb cfg1 */ 0xca06, /* mpllb cfg2 */ 0xbe40, /* mpllb cfg3 */ 0x0000, /* mpllb cfg4 */ @@ -1666,7 +1666,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_300 = { static const struct intel_c20pll_state mtl_c20_hdmi_600 = { .clock = 6000000, .tx = { 0xbe98, /* tx cfg0 */ - 0x9800, /* tx cfg1 */ + 0x8800, /* tx cfg1 */ 0x0000, /* tx cfg2 */ }, .cmn = { 0x0500, /* cmn cfg0*/ @@ -1674,8 +1674,8 @@ static const struct intel_c20pll_state mtl_c20_hdmi_600 = { 0x0000, /* cmn cfg2 */ 0x0000, /* cmn cfg3 */ }, - .mpllb = { 0x009c, /* mpllb cfg0 */ - 0x7d08, /* mpllb cfg1 */ + .mpllb = { 0x109c, /* mpllb cfg0 */ + 0x2108, /* mpllb cfg1 */ 0xca06, /* mpllb cfg2 */ 0xbe40, /* mpllb cfg3 */ 0x0000, /* mpllb cfg4 */ @@ -1691,7 +1691,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_600 = { static const struct intel_c20pll_state mtl_c20_hdmi_800 = { .clock = 8000000, .tx = { 0xbe98, /* tx cfg0 */ - 0x9800, /* tx cfg1 */ + 0x8800, /* tx cfg1 */ 0x0000, /* tx cfg2 */ }, .cmn = { 0x0500, /* cmn cfg0*/ @@ -1699,8 +1699,8 @@ static const struct intel_c20pll_state mtl_c20_hdmi_800 = { 0x0000, /* cmn cfg2 */ 0x0000, /* cmn cfg3 */ }, - .mpllb = { 0x00d0, /* mpllb cfg0 */ - 0x7d08, /* mpllb cfg1 */ + .mpllb = { 0x10d0, /* mpllb cfg0 */ + 0x2108, /* mpllb cfg1 */ 0x4a06, /* mpllb cfg2 */ 0xbe40, /* mpllb cfg3 */ 0x0000, /* mpllb cfg4 */ @@ -1716,7 +1716,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_800 = { static const struct intel_c20pll_state mtl_c20_hdmi_1000 = { .clock = 10000000, .tx = { 0xbe98, /* tx cfg0 */ - 0x9800, /* tx cfg1 */ + 0x8800, /* tx cfg1 */ 0x0000, /* tx cfg2 */ }, .cmn = { 0x0500, /* cmn cfg0*/ @@ -1725,7 +1725,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_1000 = { 0x0000, /* cmn cfg3 */ }, .mpllb = { 0x1104, /* mpllb cfg0 */ - 0x7d08, /* mpllb cfg1 */ + 0x2108, /* mpllb cfg1 */ 0x0a06, /* mpllb cfg2 */ 0xbe40, /* mpllb cfg3 */ 0x0000, /* mpllb cfg4 */ @@ -1741,7 +1741,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_1000 = { static const struct intel_c20pll_state mtl_c20_hdmi_1200 = { .clock = 12000000, .tx = { 0xbe98, /* tx cfg0 */ - 0x9800, /* tx cfg1 */ + 0x8800, /* tx cfg1 */ 0x0000, /* tx cfg2 */ }, .cmn = { 0x0500, /* cmn cfg0*/ @@ -1749,8 +1749,8 @@ static const struct intel_c20pll_state mtl_c20_hdmi_1200 = { 0x0000, /* cmn cfg2 */ 0x0000, /* cmn cfg3 */ }, - .mpllb = { 0x0138, /* mpllb cfg0 */ - 0x7d08, /* mpllb cfg1 */ + .mpllb = { 0x1138, /* mpllb cfg0 */ + 0x2108, /* mpllb cfg1 */ 0x5486, /* mpllb cfg2 */ 0xfe40, /* mpllb cfg3 */ 0x0000, /* mpllb cfg4 */
DP/eDP and HDMI C20 PHY PLL values were updated for MTL platform Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com> --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 32 ++++++++++---------- 1 file changed, 16 insertions(+), 16 deletions(-)