| Message ID | 20240226235302.41510-1-navaremanasi@chromium.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Allow for Vsync_start and Vsync_end to change in LRR | expand |
Hi Ville, Could you take a peek at this patch, as per our offline discussions, Even if VRR does not look at the Vsync start and Vsync end, we need to write to those registers to keep the state checker happy. Regards Manasi On Mon, Feb 26, 2024 at 3:53 PM Manasi Navare <navaremanasi@chromium.org> wrote: > > Since LRR mode requires panel to support VRR, any of the LRR mode > is achieved by stretching vertical front porch which also pushes > out Vsync_start and Vsync_end timings of the mode. > This allows for VSS and VSE timings to be different in case of LRR > to ensure semaless modeset/fastset to LRR mode. > > In case of VRR capable panel, it technically ignores the VSYNC because > we set Ignore_MSA bit for sink but reprogram the TRANS_VSYNC to keep > the state checker happy in case of LRR. > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Cc: Sean Paul <seanpaul@chromium.org> > Signed-off-by: Manasi Navare <navaremanasi@chromium.org> > --- > drivers/gpu/drm/i915/display/intel_display.c | 11 +++++++++-- > 1 file changed, 9 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 00ac65a14029..cd55e8840769 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -2685,6 +2685,13 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc > intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), > VBLANK_START(crtc_vblank_start - 1) | > VBLANK_END(crtc_vblank_end - 1)); > + /* > + * HW ignores TRANS_VSYNC in VRR on DP because we set Ignore MSA bit. > + * But let's write this to keepthe state checker happy. > + */ > + intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), > + VSYNC_START(adjusted_mode->crtc_vsync_start - 1) | > + VSYNC_END(adjusted_mode->crtc_vsync_end - 1)); > /* > * The double buffer latch point for TRANS_VTOTAL > * is the transcoder's undelayed vblank. > @@ -5043,11 +5050,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, > PIPE_CONF_CHECK_I(name.crtc_hsync_end); \ > PIPE_CONF_CHECK_I(name.crtc_vdisplay); \ > PIPE_CONF_CHECK_I(name.crtc_vblank_start); \ > - PIPE_CONF_CHECK_I(name.crtc_vsync_start); \ > - PIPE_CONF_CHECK_I(name.crtc_vsync_end); \ > if (!fastset || !pipe_config->update_lrr) { \ > PIPE_CONF_CHECK_I(name.crtc_vtotal); \ > PIPE_CONF_CHECK_I(name.crtc_vblank_end); \ > + PIPE_CONF_CHECK_I(name.crtc_vsync_start); \ > + PIPE_CONF_CHECK_I(name.crtc_vsync_end); \ > } \ > } while (0) > > -- > 2.44.0.rc1.240.g4c46232300-goog >
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 00ac65a14029..cd55e8840769 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2685,6 +2685,13 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), VBLANK_START(crtc_vblank_start - 1) | VBLANK_END(crtc_vblank_end - 1)); + /* + * HW ignores TRANS_VSYNC in VRR on DP because we set Ignore MSA bit. + * But let's write this to keepthe state checker happy. + */ + intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), + VSYNC_START(adjusted_mode->crtc_vsync_start - 1) | + VSYNC_END(adjusted_mode->crtc_vsync_end - 1)); /* * The double buffer latch point for TRANS_VTOTAL * is the transcoder's undelayed vblank. @@ -5043,11 +5050,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(name.crtc_hsync_end); \ PIPE_CONF_CHECK_I(name.crtc_vdisplay); \ PIPE_CONF_CHECK_I(name.crtc_vblank_start); \ - PIPE_CONF_CHECK_I(name.crtc_vsync_start); \ - PIPE_CONF_CHECK_I(name.crtc_vsync_end); \ if (!fastset || !pipe_config->update_lrr) { \ PIPE_CONF_CHECK_I(name.crtc_vtotal); \ PIPE_CONF_CHECK_I(name.crtc_vblank_end); \ + PIPE_CONF_CHECK_I(name.crtc_vsync_start); \ + PIPE_CONF_CHECK_I(name.crtc_vsync_end); \ } \ } while (0)
Since LRR mode requires panel to support VRR, any of the LRR mode is achieved by stretching vertical front porch which also pushes out Vsync_start and Vsync_end timings of the mode. This allows for VSS and VSE timings to be different in case of LRR to ensure semaless modeset/fastset to LRR mode. In case of VRR capable panel, it technically ignores the VSYNC because we set Ignore_MSA bit for sink but reprogram the TRANS_VSYNC to keep the state checker happy in case of LRR. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Sean Paul <seanpaul@chromium.org> Signed-off-by: Manasi Navare <navaremanasi@chromium.org> --- drivers/gpu/drm/i915/display/intel_display.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-)