From patchwork Wed Mar 6 01:22:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13583174 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AF1DCC54798 for ; Wed, 6 Mar 2024 01:23:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B5318112DDE; Wed, 6 Mar 2024 01:23:42 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="D06cK8sK"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id CFE3B10E7CD; Wed, 6 Mar 2024 01:23:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1709688221; x=1741224221; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RhOkg/e+CA2tiCxWfZY+FAoYX9RUdN4cq2i33DYeYm8=; b=D06cK8sK8Uu7ryuFD2v0picPIsh+MC4HGJPmNJ2dTm/IIsH2jO6lXzKF jmPySGk3YTRR9TFax1vkDDbECeDq4mBnuFrUVaQa9BXXJH0yl+gc3o7kA VftwqIDUh++dtYa5jiSJour8lV/rP3LE4wU9sU39W+hk5PfXvG0CbsC4N EddlpcLQBWEnBoK2dyw1I6Nf+HZqrtTGfmlbpc7lHCXiVVCL/8LW+Kqf0 SmLjJgvM1xmb9BBArGeGbN099kpbOPk2rUmpWGeOJ+75nqyhug6zm0tWb GZiRlxd/khMJUjdGYy8DgNuepaBSuapSlxJgmA3ger5IImTEF8nvKAjCX A==; X-IronPort-AV: E=McAfee;i="6600,9927,11004"; a="8098482" X-IronPort-AV: E=Sophos;i="6.06,207,1705392000"; d="scan'208";a="8098482" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2024 17:23:41 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,207,1705392000"; d="scan'208";a="40574614" Received: from unknown (HELO intel.com) ([10.247.118.75]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2024 17:23:34 -0800 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Joonas Lahtinen , Matt Roper , John Harrison , stable@vger.kernel.org, Andi Shyti , Andi Shyti , Tvrtko Ursulin Subject: [PATCH v4 3/3] drm/i915/gt: Enable only one CCS for compute workload Date: Wed, 6 Mar 2024 02:22:47 +0100 Message-ID: <20240306012247.246003-4-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240306012247.246003-1-andi.shyti@linux.intel.com> References: <20240306012247.246003-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Enable only one CCS engine by default with all the compute sices allocated to it. While generating the list of UABI engines to be exposed to the user, exclude any additional CCS engines beyond the first instance. This change can be tested with igt i915_query. Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement") Requires: 97aba5e46038 ("drm/i915/gt: Refactor uabi engine class/instance list creation") Signed-off-by: Andi Shyti Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Matt Roper Cc: # v6.2+ --- drivers/gpu/drm/i915/gt/intel_engine_user.c | 11 ++++++++++ drivers/gpu/drm/i915/gt/intel_gt.c | 23 +++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +++++ 3 files changed, 39 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c index 11cc06c0c785..9ef1c4ce252d 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c @@ -208,6 +208,7 @@ void intel_engines_driver_register(struct drm_i915_private *i915) struct list_head *it, *next; struct rb_node **p, *prev; LIST_HEAD(engines); + u16 uabi_ccs = 0; sort_engines(i915, &engines); @@ -244,6 +245,16 @@ void intel_engines_driver_register(struct drm_i915_private *i915) if (uabi_class > I915_LAST_UABI_ENGINE_CLASS) continue; + /* + * The load is balanced among all the available compute + * slices. Expose only the first instance of the compute + * engine. + */ + if (IS_DG2(i915) && + uabi_class == I915_ENGINE_CLASS_COMPUTE && + uabi_ccs++) + continue; + GEM_BUG_ON(uabi_class >= ARRAY_SIZE(i915->engine_uabi_class_count)); i915->engine_uabi_class_count[uabi_class]++; diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index a425db5ed3a2..0aac97439552 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -168,6 +168,26 @@ static void init_unused_rings(struct intel_gt *gt) } } +static void intel_gt_apply_ccs_mode(struct intel_gt *gt) +{ + u32 mode; + int cslice; + + if (!IS_DG2(gt->i915)) + return; + + /* Set '0' as a default CCS id to all the cslices */ + mode = 0; + + for (cslice = 0; cslice < hweight32(CCS_MASK(gt)); cslice++) + /* Write 0x7 if no CCS context dispatches to this cslice */ + if (!(CCS_MASK(gt) & BIT(cslice))) + mode |= XEHP_CCS_MODE_CSLICE(cslice, + XEHP_CCS_MODE_CSLICE_MASK); + + intel_uncore_write(gt->uncore, XEHP_CCS_MODE, mode); +} + int intel_gt_init_hw(struct intel_gt *gt) { struct drm_i915_private *i915 = gt->i915; @@ -195,6 +215,9 @@ int intel_gt_init_hw(struct intel_gt *gt) intel_gt_init_swizzling(gt); + /* Configure CCS mode */ + intel_gt_apply_ccs_mode(gt); + /* * At least 830 can leave some of the unused rings * "active" (ie. head != tail) after resume which diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index cf709f6c05ae..8224dd99c7d7 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1480,6 +1480,11 @@ #define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0) #define XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1) +#define XEHP_CCS_MODE _MMIO(0x14804) +#define XEHP_CCS_MODE_CSLICE_MASK REG_GENMASK(2, 0) /* CCS0-3 + rsvd */ +#define XEHP_CCS_MODE_CSLICE_WIDTH ilog2(XEHP_CCS_MODE_CSLICE_MASK + 1) +#define XEHP_CCS_MODE_CSLICE(cslice, ccs) (ccs << (cslice * XEHP_CCS_MODE_CSLICE_WIDTH)) + #define CHV_FUSE_GT _MMIO(VLV_GUNIT_BASE + 0x2168) #define CHV_FGT_DISABLE_SS0 (1 << 10) #define CHV_FGT_DISABLE_SS1 (1 << 11)