| Message ID | 20240320201152.3487892-6-imre.deak@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/dp: Few MTL/DSC and a UHBR monitor fix | expand |
On 3/21/2024 1:41 AM, Imre Deak wrote: > The DPT/DSC bpp limit should be accounted for on MTL platforms as well, > do so. > > Bspec: 49259 > > Signed-off-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index 79f34be5c89da..40660dc5edb45 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -56,7 +56,7 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp > struct intel_crtc_state *crtc_state, > bool dsc) > { > - if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 14 && dsc) { Should this be DISPLAY_VER() <= 14 to include MTL? For DISPLAY_VER 20, is there another check? in Bspec:68912 it mentions output bpp * pixel clock < DDICLK * 144 bits Regards, Ankit > + if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 20 && dsc) { > int output_bpp = bpp; > int symbol_clock = intel_dp_link_symbol_clock(crtc_state->port_clock); > int available_bw = mul_u32_u32(symbol_clock * 72,
On 3/26/2024 3:47 PM, Nautiyal, Ankit K wrote: > > On 3/21/2024 1:41 AM, Imre Deak wrote: >> The DPT/DSC bpp limit should be accounted for on MTL platforms as well, >> do so. >> >> Bspec: 49259 >> >> Signed-off-by: Imre Deak <imre.deak@intel.com> >> --- >> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c >> b/drivers/gpu/drm/i915/display/intel_dp_mst.c >> index 79f34be5c89da..40660dc5edb45 100644 >> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c >> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c >> @@ -56,7 +56,7 @@ static int intel_dp_mst_check_constraints(struct >> drm_i915_private *i915, int bpp >> struct intel_crtc_state *crtc_state, >> bool dsc) >> { >> - if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 14 && >> dsc) { > > Should this be DISPLAY_VER() <= 14 to include MTL? > > For DISPLAY_VER 20, is there another check? > > in Bspec:68912 it mentions output bpp * pixel clock < DDICLK * 144 bits Please ignore the above, I see you are addressing this in next patch. The patch looks good as it is. Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Regards, Ankit > > > Regards, > > Ankit > >> + if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 20 && >> dsc) { >> int output_bpp = bpp; >> int symbol_clock = >> intel_dp_link_symbol_clock(crtc_state->port_clock); >> int available_bw = mul_u32_u32(symbol_clock * 72,
On Tue, Mar 26, 2024 at 03:47:05PM +0530, Nautiyal, Ankit K wrote: > > On 3/21/2024 1:41 AM, Imre Deak wrote: > > The DPT/DSC bpp limit should be accounted for on MTL platforms as well, > > do so. > > > > Bspec: 49259 > > > > Signed-off-by: Imre Deak <imre.deak@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > index 79f34be5c89da..40660dc5edb45 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > @@ -56,7 +56,7 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp > > struct intel_crtc_state *crtc_state, > > bool dsc) > > { > > - if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 14 && dsc) { > > Should this be DISPLAY_VER() <= 14 to include MTL? The actual change is the DISPLAY_VER() < 20 below, which is the usual way in the driver (AFAIU) to check for an upper bound. > For DISPLAY_VER 20, is there another check? > > in Bspec:68912 it mentions output bpp * pixel clock < DDICLK * 144 bits Yes LNL is different, but there this DPT limit should never be a bottleneck. Ville has an idea to abstract this more, but this patchset keeps things as-is, skipping the check on LNL+. > Regards, > > Ankit > > > + if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 20 && dsc) { > > int output_bpp = bpp; > > int symbol_clock = intel_dp_link_symbol_clock(crtc_state->port_clock); > > int available_bw = mul_u32_u32(symbol_clock * 72,
On 3/26/2024 5:41 PM, Imre Deak wrote: > On Tue, Mar 26, 2024 at 03:47:05PM +0530, Nautiyal, Ankit K wrote: >> On 3/21/2024 1:41 AM, Imre Deak wrote: >>> The DPT/DSC bpp limit should be accounted for on MTL platforms as well, >>> do so. >>> >>> Bspec: 49259 >>> >>> Signed-off-by: Imre Deak <imre.deak@intel.com> >>> --- >>> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- >>> 1 file changed, 1 insertion(+), 1 deletion(-) >>> >>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c >>> index 79f34be5c89da..40660dc5edb45 100644 >>> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c >>> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c >>> @@ -56,7 +56,7 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp >>> struct intel_crtc_state *crtc_state, >>> bool dsc) >>> { >>> - if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 14 && dsc) { >> Should this be DISPLAY_VER() <= 14 to include MTL? > The actual change is the DISPLAY_VER() < 20 below, which is the usual > way in the driver (AFAIU) to check for an upper bound. Makes sense. > >> For DISPLAY_VER 20, is there another check? >> >> in Bspec:68912 it mentions output bpp * pixel clock < DDICLK * 144 bits > Yes LNL is different, but there this DPT limit should never be a > bottleneck. Ville has an idea to abstract this more, but this patchset > keeps things as-is, skipping the check on LNL+. Agreed. Bspec indeed mentions the same thing, and its mentioned appropriately in the next patch. Regards, Ankit > >> Regards, >> >> Ankit >> >>> + if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 20 && dsc) { >>> int output_bpp = bpp; >>> int symbol_clock = intel_dp_link_symbol_clock(crtc_state->port_clock); >>> int available_bw = mul_u32_u32(symbol_clock * 72,
Hi Imre, While we are adding these checks here for DSC for MST, I see that in intel_dp_mst_mode_valid_ctx() we still check against DISPLAY_VER() > 10 for checking for DSC where as in all other places we rely on runtime has_dsc and check for HAS_DSC(), can we fix that and use HAS_DSC() in this function as well as part of this series that in general fixes some DSC issues? Manasi On Tue, Mar 26, 2024 at 5:59 AM Nautiyal, Ankit K <ankit.k.nautiyal@intel.com> wrote: > > > On 3/26/2024 5:41 PM, Imre Deak wrote: > > On Tue, Mar 26, 2024 at 03:47:05PM +0530, Nautiyal, Ankit K wrote: > >> On 3/21/2024 1:41 AM, Imre Deak wrote: > >>> The DPT/DSC bpp limit should be accounted for on MTL platforms as well, > >>> do so. > >>> > >>> Bspec: 49259 > >>> > >>> Signed-off-by: Imre Deak <imre.deak@intel.com> > >>> --- > >>> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- > >>> 1 file changed, 1 insertion(+), 1 deletion(-) > >>> > >>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > >>> index 79f34be5c89da..40660dc5edb45 100644 > >>> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > >>> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > >>> @@ -56,7 +56,7 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp > >>> struct intel_crtc_state *crtc_state, > >>> bool dsc) > >>> { > >>> - if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 14 && dsc) { > >> Should this be DISPLAY_VER() <= 14 to include MTL? > > The actual change is the DISPLAY_VER() < 20 below, which is the usual > > way in the driver (AFAIU) to check for an upper bound. > > Makes sense. > > > > >> For DISPLAY_VER 20, is there another check? > >> > >> in Bspec:68912 it mentions output bpp * pixel clock < DDICLK * 144 bits > > Yes LNL is different, but there this DPT limit should never be a > > bottleneck. Ville has an idea to abstract this more, but this patchset > > keeps things as-is, skipping the check on LNL+. > > Agreed. Bspec indeed mentions the same thing, and its mentioned > appropriately in the next patch. > > Regards, > > Ankit > > > > >> Regards, > >> > >> Ankit > >> > >>> + if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 20 && dsc) { > >>> int output_bpp = bpp; > >>> int symbol_clock = intel_dp_link_symbol_clock(crtc_state->port_clock); > >>> int available_bw = mul_u32_u32(symbol_clock * 72,
On Fri, Mar 29, 2024 at 11:39:39AM -0700, Manasi Navare wrote: > Hi Imre, > > While we are adding these checks here for DSC for MST, I see that in > intel_dp_mst_mode_valid_ctx() we still check against DISPLAY_VER() > > 10 for checking for DSC where as in all other places we rely on > runtime has_dsc and check for HAS_DSC(), can we fix that and use > HAS_DSC() in this function as well as part of this series that in > general fixes some DSC issues? The check in intel_dp_mst_check_constraints() this patch changes is not about whether a platform supports DSC or not, rather if the platform has a DSC/DPT interface limit that needs to be checked. The caller has already determined that DSC is supported by the platform and it's needed for the given mode being computed (dsc==true). > > Manasi > > On Tue, Mar 26, 2024 at 5:59 AM Nautiyal, Ankit K > <ankit.k.nautiyal@intel.com> wrote: > > > > > > On 3/26/2024 5:41 PM, Imre Deak wrote: > > > On Tue, Mar 26, 2024 at 03:47:05PM +0530, Nautiyal, Ankit K wrote: > > >> On 3/21/2024 1:41 AM, Imre Deak wrote: > > >>> The DPT/DSC bpp limit should be accounted for on MTL platforms as well, > > >>> do so. > > >>> > > >>> Bspec: 49259 > > >>> > > >>> Signed-off-by: Imre Deak <imre.deak@intel.com> > > >>> --- > > >>> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- > > >>> 1 file changed, 1 insertion(+), 1 deletion(-) > > >>> > > >>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > >>> index 79f34be5c89da..40660dc5edb45 100644 > > >>> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > > >>> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > >>> @@ -56,7 +56,7 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp > > >>> struct intel_crtc_state *crtc_state, > > >>> bool dsc) > > >>> { > > >>> - if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 14 && dsc) { > > >> Should this be DISPLAY_VER() <= 14 to include MTL? > > > The actual change is the DISPLAY_VER() < 20 below, which is the usual > > > way in the driver (AFAIU) to check for an upper bound. > > > > Makes sense. > > > > > > > >> For DISPLAY_VER 20, is there another check? > > >> > > >> in Bspec:68912 it mentions output bpp * pixel clock < DDICLK * 144 bits > > > Yes LNL is different, but there this DPT limit should never be a > > > bottleneck. Ville has an idea to abstract this more, but this patchset > > > keeps things as-is, skipping the check on LNL+. > > > > Agreed. Bspec indeed mentions the same thing, and its mentioned > > appropriately in the next patch. > > > > Regards, > > > > Ankit > > > > > > > >> Regards, > > >> > > >> Ankit > > >> > > >>> + if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 20 && dsc) { > > >>> int output_bpp = bpp; > > >>> int symbol_clock = intel_dp_link_symbol_clock(crtc_state->port_clock); > > >>> int available_bw = mul_u32_u32(symbol_clock * 72,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 79f34be5c89da..40660dc5edb45 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -56,7 +56,7 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp struct intel_crtc_state *crtc_state, bool dsc) { - if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 14 && dsc) { + if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 20 && dsc) { int output_bpp = bpp; int symbol_clock = intel_dp_link_symbol_clock(crtc_state->port_clock); int available_bw = mul_u32_u32(symbol_clock * 72,
The DPT/DSC bpp limit should be accounted for on MTL platforms as well, do so. Bspec: 49259 Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)