From patchwork Wed Mar 27 15:56:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13606890 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 382E1C47DD9 for ; Wed, 27 Mar 2024 15:57:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 92BEB10EAE2; Wed, 27 Mar 2024 15:57:40 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="N9SAWM2v"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id ED4DC10E619; Wed, 27 Mar 2024 15:57:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1711555059; x=1743091059; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WKS4G/JZZc32wBQOFU9VUnZxgHcH9+WC0RJw3zMDNd8=; b=N9SAWM2vzAnrZkHvZjK2brgTedZgn7HmAvOEwla86ByJ5rdN2FAWecS9 /7q6tmpWzgYb7u7VNfBDQyN6Uf0pWuSYBZsuVNN/HO7IJl/FEJfmyI8YW GscUrverW60KPh19n7/hsIs3zWVWnP4BKuF8oMCA/DRJ2S7B26Ro3EI3A AS/UADJL1F7Xxe4VSVGlhq8ZGsDL1vEFD8UKeods0cidzIsdqaoSG85Rn 1OOKZfjij1IgLl0wHReIr8vvW9imaNUUWMBpwtPcCNtneOH29C8V+xbYm axE2/Ety8/Rkc8wP70ijlKRqwCR46tATAd8SC05iKBwiGKy8GRnzs9SXY w==; X-CSE-ConnectionGUID: rjmIF+qLSLizNsEVBY6Ong== X-CSE-MsgGUID: bpIHatuRT/K2vU395uQlUw== X-IronPort-AV: E=McAfee;i="6600,9927,11026"; a="7271763" X-IronPort-AV: E=Sophos;i="6.07,159,1708416000"; d="scan'208";a="7271763" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Mar 2024 08:57:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,159,1708416000"; d="scan'208";a="16787647" Received: from unknown (HELO intel.com) ([10.247.118.215]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Mar 2024 08:57:23 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Joonas Lahtinen , Matt Roper , John Harrison , Tvrtko Ursulin , Michal Mrozek , stable@vger.kernel.org, Andi Shyti , Andi Shyti Subject: [PATCH v7 2/3] drm/i915/gt: Do not generate the command streamer for all the CCS Date: Wed, 27 Mar 2024 16:56:18 +0100 Message-ID: <20240327155622.538140-3-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240327155622.538140-1-andi.shyti@linux.intel.com> References: <20240327155622.538140-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We want a fixed load CCS balancing consisting in all slices sharing one single user engine. For this reason do not create the intel_engine_cs structure with its dedicated command streamer for CCS slices beyond the first. Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement") Signed-off-by: Andi Shyti Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Matt Roper Cc: # v6.2+ Acked-by: Michal Mrozek --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index f553cf4e6449..47c4a69e854c 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -908,6 +908,21 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt) info->engine_mask &= ~BIT(GSC0); } + /* + * Do not create the command streamer for CCS slices beyond the first. + * All the workload submitted to the first engine will be shared among + * all the slices. + * + * Once the user will be allowed to customize the CCS mode, then this + * check needs to be removed. + */ + if (IS_DG2(gt->i915)) { + intel_engine_mask_t first_ccs = BIT((CCS0 + __ffs(CCS_MASK(gt)))); + intel_engine_mask_t all_ccs = CCS_MASK(gt) << CCS0; + + info->engine_mask &= ~(all_ccs &= ~first_ccs); + } + return info->engine_mask; }