| Message ID | 20240327174544.983-4-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Implemnt vblank sycnhronized mbus joining changes | expand |
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville > Syrjala > Sent: Wednesday, March 27, 2024 11:16 PM > To: intel-gfx@lists.freedesktop.org > Subject: [PATCH 03/13] drm/i915/cdclk: Drop tgl/dg2 cdclk bump hacks > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > No ever figured out why bumping the cdclk helped with whatever issue we were > having at the time. > Remove the hacks and start from scratch so that we can actually see if any > problems still remain. Yeah, there can be cases where bumping the clock can help avoid the latency and suppress an issue. However, this is not recommended by hardware and we should be able to drive the display as per the calculated clock based on pixel rate. Having said that, we should brace ourselves for the issues which it was fixing. Ok to drop the hack, Reviewed-by: Uma Shankar <uma.shankar@intel.com> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 19 ------------------- > 1 file changed, 19 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c > b/drivers/gpu/drm/i915/display/intel_cdclk.c > index 504c5cbbcfff..99d2657f29a7 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -2802,25 +2802,6 @@ int intel_crtc_compute_min_cdclk(const struct > intel_crtc_state *crtc_state) > if (crtc_state->dsc.compression_enable) > min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state)); > > - /* > - * HACK. Currently for TGL/DG2 platforms we calculate > - * min_cdclk initially based on pixel_rate divided > - * by 2, accounting for also plane requirements, > - * however in some cases the lowest possible CDCLK > - * doesn't work and causing the underruns. > - * Explicitly stating here that this seems to be currently > - * rather a Hack, than final solution. > - */ > - if (IS_TIGERLAKE(dev_priv) || IS_DG2(dev_priv)) { > - /* > - * Clamp to max_cdclk_freq in case pixel rate is higher, > - * in order not to break an 8K, but still leave W/A at place. > - */ > - min_cdclk = max_t(int, min_cdclk, > - min_t(int, crtc_state->pixel_rate, > - dev_priv- > >display.cdclk.max_cdclk_freq)); > - } > - > return min_cdclk; > } > > -- > 2.43.2
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 504c5cbbcfff..99d2657f29a7 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2802,25 +2802,6 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) if (crtc_state->dsc.compression_enable) min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state)); - /* - * HACK. Currently for TGL/DG2 platforms we calculate - * min_cdclk initially based on pixel_rate divided - * by 2, accounting for also plane requirements, - * however in some cases the lowest possible CDCLK - * doesn't work and causing the underruns. - * Explicitly stating here that this seems to be currently - * rather a Hack, than final solution. - */ - if (IS_TIGERLAKE(dev_priv) || IS_DG2(dev_priv)) { - /* - * Clamp to max_cdclk_freq in case pixel rate is higher, - * in order not to break an 8K, but still leave W/A at place. - */ - min_cdclk = max_t(int, min_cdclk, - min_t(int, crtc_state->pixel_rate, - dev_priv->display.cdclk.max_cdclk_freq)); - } - return min_cdclk; }