diff mbox series

[06/13] drm/i915: Relocate intel_mbus_dbox_update()

Message ID 20240327174544.983-7-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: Implemnt vblank sycnhronized mbus joining changes | expand

Commit Message

Ville Syrjälä March 27, 2024, 5:45 p.m. UTC
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

intel_mbus_dbox_update() will become static soon. Relocate it
into a place that avoids having to add a forward declaration
for it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 166 +++++++++----------
 1 file changed, 83 insertions(+), 83 deletions(-)

Comments

Shankar, Uma March 28, 2024, 11:54 a.m. UTC | #1
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, March 27, 2024 11:16 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 06/13] drm/i915: Relocate intel_mbus_dbox_update()
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> intel_mbus_dbox_update() will become static soon. Relocate it into a place that
> avoids having to add a forward declaration for it.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 166 +++++++++----------
>  1 file changed, 83 insertions(+), 83 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index f582992592c1..6bd3fec0aa56 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3540,6 +3540,89 @@ int intel_dbuf_init(struct drm_i915_private *i915)
>  	return 0;
>  }
> 
> +static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8
> +active_pipes) {
> +	switch (pipe) {
> +	case PIPE_A:
> +		return !(active_pipes & BIT(PIPE_D));
> +	case PIPE_D:
> +		return !(active_pipes & BIT(PIPE_A));
> +	case PIPE_B:
> +		return !(active_pipes & BIT(PIPE_C));
> +	case PIPE_C:
> +		return !(active_pipes & BIT(PIPE_B));
> +	default: /* to suppress compiler warning */
> +		MISSING_CASE(pipe);
> +		break;
> +	}
> +
> +	return false;
> +}
> +
> +void intel_mbus_dbox_update(struct intel_atomic_state *state) {
> +	struct drm_i915_private *i915 = to_i915(state->base.dev);
> +	const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
> +	const struct intel_crtc *crtc;
> +	u32 val = 0;
> +
> +	if (DISPLAY_VER(i915) < 11)
> +		return;
> +
> +	new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
> +	old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
> +	if (!new_dbuf_state ||
> +	    (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
> +	     new_dbuf_state->active_pipes == old_dbuf_state->active_pipes))
> +		return;
> +
> +	if (DISPLAY_VER(i915) >= 14)
> +		val |= MBUS_DBOX_I_CREDIT(2);
> +
> +	if (DISPLAY_VER(i915) >= 12) {
> +		val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);
> +		val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);
> +		val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN;
> +	}
> +
> +	if (DISPLAY_VER(i915) >= 14)
> +		val |= new_dbuf_state->joined_mbus ?
> MBUS_DBOX_A_CREDIT(12) :
> +						     MBUS_DBOX_A_CREDIT(8);
> +	else if (IS_ALDERLAKE_P(i915))
> +		/* Wa_22010947358:adl-p */
> +		val |= new_dbuf_state->joined_mbus ?
> MBUS_DBOX_A_CREDIT(6) :
> +						     MBUS_DBOX_A_CREDIT(4);
> +	else
> +		val |= MBUS_DBOX_A_CREDIT(2);
> +
> +	if (DISPLAY_VER(i915) >= 14) {
> +		val |= MBUS_DBOX_B_CREDIT(0xA);
> +	} else if (IS_ALDERLAKE_P(i915)) {
> +		val |= MBUS_DBOX_BW_CREDIT(2);
> +		val |= MBUS_DBOX_B_CREDIT(8);
> +	} else if (DISPLAY_VER(i915) >= 12) {
> +		val |= MBUS_DBOX_BW_CREDIT(2);
> +		val |= MBUS_DBOX_B_CREDIT(12);
> +	} else {
> +		val |= MBUS_DBOX_BW_CREDIT(1);
> +		val |= MBUS_DBOX_B_CREDIT(8);
> +	}
> +
> +	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, new_dbuf_state-
> >active_pipes) {
> +		u32 pipe_val = val;
> +
> +		if (DISPLAY_VER(i915) >= 14) {
> +			if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe,
> +							      new_dbuf_state-
> >active_pipes))
> +				pipe_val |= MBUS_DBOX_BW_8CREDITS_MTL;
> +			else
> +				pipe_val |= MBUS_DBOX_BW_4CREDITS_MTL;
> +		}
> +
> +		intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe),
> pipe_val);
> +	}
> +}
> +
>  int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, u8
> ratio)  {
>  	struct intel_dbuf_state *dbuf_state;
> @@ -3657,89 +3740,6 @@ void intel_dbuf_post_plane_update(struct
> intel_atomic_state *state)
>  				new_dbuf_state->enabled_slices);
>  }
> 
> -static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8
> active_pipes) -{
> -	switch (pipe) {
> -	case PIPE_A:
> -		return !(active_pipes & BIT(PIPE_D));
> -	case PIPE_D:
> -		return !(active_pipes & BIT(PIPE_A));
> -	case PIPE_B:
> -		return !(active_pipes & BIT(PIPE_C));
> -	case PIPE_C:
> -		return !(active_pipes & BIT(PIPE_B));
> -	default: /* to suppress compiler warning */
> -		MISSING_CASE(pipe);
> -		break;
> -	}
> -
> -	return false;
> -}
> -
> -void intel_mbus_dbox_update(struct intel_atomic_state *state) -{
> -	struct drm_i915_private *i915 = to_i915(state->base.dev);
> -	const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
> -	const struct intel_crtc *crtc;
> -	u32 val = 0;
> -
> -	if (DISPLAY_VER(i915) < 11)
> -		return;
> -
> -	new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
> -	old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
> -	if (!new_dbuf_state ||
> -	    (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
> -	     new_dbuf_state->active_pipes == old_dbuf_state->active_pipes))
> -		return;
> -
> -	if (DISPLAY_VER(i915) >= 14)
> -		val |= MBUS_DBOX_I_CREDIT(2);
> -
> -	if (DISPLAY_VER(i915) >= 12) {
> -		val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);
> -		val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);
> -		val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN;
> -	}
> -
> -	if (DISPLAY_VER(i915) >= 14)
> -		val |= new_dbuf_state->joined_mbus ?
> MBUS_DBOX_A_CREDIT(12) :
> -						     MBUS_DBOX_A_CREDIT(8);
> -	else if (IS_ALDERLAKE_P(i915))
> -		/* Wa_22010947358:adl-p */
> -		val |= new_dbuf_state->joined_mbus ?
> MBUS_DBOX_A_CREDIT(6) :
> -						     MBUS_DBOX_A_CREDIT(4);
> -	else
> -		val |= MBUS_DBOX_A_CREDIT(2);
> -
> -	if (DISPLAY_VER(i915) >= 14) {
> -		val |= MBUS_DBOX_B_CREDIT(0xA);
> -	} else if (IS_ALDERLAKE_P(i915)) {
> -		val |= MBUS_DBOX_BW_CREDIT(2);
> -		val |= MBUS_DBOX_B_CREDIT(8);
> -	} else if (DISPLAY_VER(i915) >= 12) {
> -		val |= MBUS_DBOX_BW_CREDIT(2);
> -		val |= MBUS_DBOX_B_CREDIT(12);
> -	} else {
> -		val |= MBUS_DBOX_BW_CREDIT(1);
> -		val |= MBUS_DBOX_B_CREDIT(8);
> -	}
> -
> -	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, new_dbuf_state-
> >active_pipes) {
> -		u32 pipe_val = val;
> -
> -		if (DISPLAY_VER(i915) >= 14) {
> -			if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe,
> -							      new_dbuf_state-
> >active_pipes))
> -				pipe_val |= MBUS_DBOX_BW_8CREDITS_MTL;
> -			else
> -				pipe_val |= MBUS_DBOX_BW_4CREDITS_MTL;
> -		}
> -
> -		intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe),
> pipe_val);
> -	}
> -}
> -
>  static int skl_watermark_ipc_status_show(struct seq_file *m, void *data)  {
>  	struct drm_i915_private *i915 = m->private;
> --
> 2.43.2
Gustavo Sousa March 29, 2024, 6:28 p.m. UTC | #2
Quoting Ville Syrjala (2024-03-27 14:45:37-03:00)
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>intel_mbus_dbox_update() will become static soon. Relocate it
>into a place that avoids having to add a forward declaration
>for it.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>

>---
> drivers/gpu/drm/i915/display/skl_watermark.c | 166 +++++++++----------
> 1 file changed, 83 insertions(+), 83 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
>index f582992592c1..6bd3fec0aa56 100644
>--- a/drivers/gpu/drm/i915/display/skl_watermark.c
>+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
>@@ -3540,6 +3540,89 @@ int intel_dbuf_init(struct drm_i915_private *i915)
>         return 0;
> }
> 
>+static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes)
>+{
>+        switch (pipe) {
>+        case PIPE_A:
>+                return !(active_pipes & BIT(PIPE_D));
>+        case PIPE_D:
>+                return !(active_pipes & BIT(PIPE_A));
>+        case PIPE_B:
>+                return !(active_pipes & BIT(PIPE_C));
>+        case PIPE_C:
>+                return !(active_pipes & BIT(PIPE_B));
>+        default: /* to suppress compiler warning */
>+                MISSING_CASE(pipe);
>+                break;
>+        }
>+
>+        return false;
>+}
>+
>+void intel_mbus_dbox_update(struct intel_atomic_state *state)
>+{
>+        struct drm_i915_private *i915 = to_i915(state->base.dev);
>+        const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
>+        const struct intel_crtc *crtc;
>+        u32 val = 0;
>+
>+        if (DISPLAY_VER(i915) < 11)
>+                return;
>+
>+        new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
>+        old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
>+        if (!new_dbuf_state ||
>+            (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
>+             new_dbuf_state->active_pipes == old_dbuf_state->active_pipes))
>+                return;
>+
>+        if (DISPLAY_VER(i915) >= 14)
>+                val |= MBUS_DBOX_I_CREDIT(2);
>+
>+        if (DISPLAY_VER(i915) >= 12) {
>+                val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);
>+                val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);
>+                val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN;
>+        }
>+
>+        if (DISPLAY_VER(i915) >= 14)
>+                val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(12) :
>+                                                     MBUS_DBOX_A_CREDIT(8);
>+        else if (IS_ALDERLAKE_P(i915))
>+                /* Wa_22010947358:adl-p */
>+                val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(6) :
>+                                                     MBUS_DBOX_A_CREDIT(4);
>+        else
>+                val |= MBUS_DBOX_A_CREDIT(2);
>+
>+        if (DISPLAY_VER(i915) >= 14) {
>+                val |= MBUS_DBOX_B_CREDIT(0xA);
>+        } else if (IS_ALDERLAKE_P(i915)) {
>+                val |= MBUS_DBOX_BW_CREDIT(2);
>+                val |= MBUS_DBOX_B_CREDIT(8);
>+        } else if (DISPLAY_VER(i915) >= 12) {
>+                val |= MBUS_DBOX_BW_CREDIT(2);
>+                val |= MBUS_DBOX_B_CREDIT(12);
>+        } else {
>+                val |= MBUS_DBOX_BW_CREDIT(1);
>+                val |= MBUS_DBOX_B_CREDIT(8);
>+        }
>+
>+        for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, new_dbuf_state->active_pipes) {
>+                u32 pipe_val = val;
>+
>+                if (DISPLAY_VER(i915) >= 14) {
>+                        if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe,
>+                                                              new_dbuf_state->active_pipes))
>+                                pipe_val |= MBUS_DBOX_BW_8CREDITS_MTL;
>+                        else
>+                                pipe_val |= MBUS_DBOX_BW_4CREDITS_MTL;
>+                }
>+
>+                intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), pipe_val);
>+        }
>+}
>+
> int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, u8 ratio)
> {
>         struct intel_dbuf_state *dbuf_state;
>@@ -3657,89 +3740,6 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
>                                 new_dbuf_state->enabled_slices);
> }
> 
>-static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes)
>-{
>-        switch (pipe) {
>-        case PIPE_A:
>-                return !(active_pipes & BIT(PIPE_D));
>-        case PIPE_D:
>-                return !(active_pipes & BIT(PIPE_A));
>-        case PIPE_B:
>-                return !(active_pipes & BIT(PIPE_C));
>-        case PIPE_C:
>-                return !(active_pipes & BIT(PIPE_B));
>-        default: /* to suppress compiler warning */
>-                MISSING_CASE(pipe);
>-                break;
>-        }
>-
>-        return false;
>-}
>-
>-void intel_mbus_dbox_update(struct intel_atomic_state *state)
>-{
>-        struct drm_i915_private *i915 = to_i915(state->base.dev);
>-        const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
>-        const struct intel_crtc *crtc;
>-        u32 val = 0;
>-
>-        if (DISPLAY_VER(i915) < 11)
>-                return;
>-
>-        new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
>-        old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
>-        if (!new_dbuf_state ||
>-            (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
>-             new_dbuf_state->active_pipes == old_dbuf_state->active_pipes))
>-                return;
>-
>-        if (DISPLAY_VER(i915) >= 14)
>-                val |= MBUS_DBOX_I_CREDIT(2);
>-
>-        if (DISPLAY_VER(i915) >= 12) {
>-                val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);
>-                val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);
>-                val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN;
>-        }
>-
>-        if (DISPLAY_VER(i915) >= 14)
>-                val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(12) :
>-                                                     MBUS_DBOX_A_CREDIT(8);
>-        else if (IS_ALDERLAKE_P(i915))
>-                /* Wa_22010947358:adl-p */
>-                val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(6) :
>-                                                     MBUS_DBOX_A_CREDIT(4);
>-        else
>-                val |= MBUS_DBOX_A_CREDIT(2);
>-
>-        if (DISPLAY_VER(i915) >= 14) {
>-                val |= MBUS_DBOX_B_CREDIT(0xA);
>-        } else if (IS_ALDERLAKE_P(i915)) {
>-                val |= MBUS_DBOX_BW_CREDIT(2);
>-                val |= MBUS_DBOX_B_CREDIT(8);
>-        } else if (DISPLAY_VER(i915) >= 12) {
>-                val |= MBUS_DBOX_BW_CREDIT(2);
>-                val |= MBUS_DBOX_B_CREDIT(12);
>-        } else {
>-                val |= MBUS_DBOX_BW_CREDIT(1);
>-                val |= MBUS_DBOX_B_CREDIT(8);
>-        }
>-
>-        for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, new_dbuf_state->active_pipes) {
>-                u32 pipe_val = val;
>-
>-                if (DISPLAY_VER(i915) >= 14) {
>-                        if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe,
>-                                                              new_dbuf_state->active_pipes))
>-                                pipe_val |= MBUS_DBOX_BW_8CREDITS_MTL;
>-                        else
>-                                pipe_val |= MBUS_DBOX_BW_4CREDITS_MTL;
>-                }
>-
>-                intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), pipe_val);
>-        }
>-}
>-
> static int skl_watermark_ipc_status_show(struct seq_file *m, void *data)
> {
>         struct drm_i915_private *i915 = m->private;
>-- 
>2.43.2
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index f582992592c1..6bd3fec0aa56 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3540,6 +3540,89 @@  int intel_dbuf_init(struct drm_i915_private *i915)
 	return 0;
 }
 
+static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes)
+{
+	switch (pipe) {
+	case PIPE_A:
+		return !(active_pipes & BIT(PIPE_D));
+	case PIPE_D:
+		return !(active_pipes & BIT(PIPE_A));
+	case PIPE_B:
+		return !(active_pipes & BIT(PIPE_C));
+	case PIPE_C:
+		return !(active_pipes & BIT(PIPE_B));
+	default: /* to suppress compiler warning */
+		MISSING_CASE(pipe);
+		break;
+	}
+
+	return false;
+}
+
+void intel_mbus_dbox_update(struct intel_atomic_state *state)
+{
+	struct drm_i915_private *i915 = to_i915(state->base.dev);
+	const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
+	const struct intel_crtc *crtc;
+	u32 val = 0;
+
+	if (DISPLAY_VER(i915) < 11)
+		return;
+
+	new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
+	old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
+	if (!new_dbuf_state ||
+	    (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
+	     new_dbuf_state->active_pipes == old_dbuf_state->active_pipes))
+		return;
+
+	if (DISPLAY_VER(i915) >= 14)
+		val |= MBUS_DBOX_I_CREDIT(2);
+
+	if (DISPLAY_VER(i915) >= 12) {
+		val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);
+		val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);
+		val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN;
+	}
+
+	if (DISPLAY_VER(i915) >= 14)
+		val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(12) :
+						     MBUS_DBOX_A_CREDIT(8);
+	else if (IS_ALDERLAKE_P(i915))
+		/* Wa_22010947358:adl-p */
+		val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(6) :
+						     MBUS_DBOX_A_CREDIT(4);
+	else
+		val |= MBUS_DBOX_A_CREDIT(2);
+
+	if (DISPLAY_VER(i915) >= 14) {
+		val |= MBUS_DBOX_B_CREDIT(0xA);
+	} else if (IS_ALDERLAKE_P(i915)) {
+		val |= MBUS_DBOX_BW_CREDIT(2);
+		val |= MBUS_DBOX_B_CREDIT(8);
+	} else if (DISPLAY_VER(i915) >= 12) {
+		val |= MBUS_DBOX_BW_CREDIT(2);
+		val |= MBUS_DBOX_B_CREDIT(12);
+	} else {
+		val |= MBUS_DBOX_BW_CREDIT(1);
+		val |= MBUS_DBOX_B_CREDIT(8);
+	}
+
+	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, new_dbuf_state->active_pipes) {
+		u32 pipe_val = val;
+
+		if (DISPLAY_VER(i915) >= 14) {
+			if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe,
+							      new_dbuf_state->active_pipes))
+				pipe_val |= MBUS_DBOX_BW_8CREDITS_MTL;
+			else
+				pipe_val |= MBUS_DBOX_BW_4CREDITS_MTL;
+		}
+
+		intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), pipe_val);
+	}
+}
+
 int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, u8 ratio)
 {
 	struct intel_dbuf_state *dbuf_state;
@@ -3657,89 +3740,6 @@  void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
 				new_dbuf_state->enabled_slices);
 }
 
-static bool xelpdp_is_only_pipe_per_dbuf_bank(enum pipe pipe, u8 active_pipes)
-{
-	switch (pipe) {
-	case PIPE_A:
-		return !(active_pipes & BIT(PIPE_D));
-	case PIPE_D:
-		return !(active_pipes & BIT(PIPE_A));
-	case PIPE_B:
-		return !(active_pipes & BIT(PIPE_C));
-	case PIPE_C:
-		return !(active_pipes & BIT(PIPE_B));
-	default: /* to suppress compiler warning */
-		MISSING_CASE(pipe);
-		break;
-	}
-
-	return false;
-}
-
-void intel_mbus_dbox_update(struct intel_atomic_state *state)
-{
-	struct drm_i915_private *i915 = to_i915(state->base.dev);
-	const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
-	const struct intel_crtc *crtc;
-	u32 val = 0;
-
-	if (DISPLAY_VER(i915) < 11)
-		return;
-
-	new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
-	old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
-	if (!new_dbuf_state ||
-	    (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
-	     new_dbuf_state->active_pipes == old_dbuf_state->active_pipes))
-		return;
-
-	if (DISPLAY_VER(i915) >= 14)
-		val |= MBUS_DBOX_I_CREDIT(2);
-
-	if (DISPLAY_VER(i915) >= 12) {
-		val |= MBUS_DBOX_B2B_TRANSACTIONS_MAX(16);
-		val |= MBUS_DBOX_B2B_TRANSACTIONS_DELAY(1);
-		val |= MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN;
-	}
-
-	if (DISPLAY_VER(i915) >= 14)
-		val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(12) :
-						     MBUS_DBOX_A_CREDIT(8);
-	else if (IS_ALDERLAKE_P(i915))
-		/* Wa_22010947358:adl-p */
-		val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(6) :
-						     MBUS_DBOX_A_CREDIT(4);
-	else
-		val |= MBUS_DBOX_A_CREDIT(2);
-
-	if (DISPLAY_VER(i915) >= 14) {
-		val |= MBUS_DBOX_B_CREDIT(0xA);
-	} else if (IS_ALDERLAKE_P(i915)) {
-		val |= MBUS_DBOX_BW_CREDIT(2);
-		val |= MBUS_DBOX_B_CREDIT(8);
-	} else if (DISPLAY_VER(i915) >= 12) {
-		val |= MBUS_DBOX_BW_CREDIT(2);
-		val |= MBUS_DBOX_B_CREDIT(12);
-	} else {
-		val |= MBUS_DBOX_BW_CREDIT(1);
-		val |= MBUS_DBOX_B_CREDIT(8);
-	}
-
-	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, new_dbuf_state->active_pipes) {
-		u32 pipe_val = val;
-
-		if (DISPLAY_VER(i915) >= 14) {
-			if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe,
-							      new_dbuf_state->active_pipes))
-				pipe_val |= MBUS_DBOX_BW_8CREDITS_MTL;
-			else
-				pipe_val |= MBUS_DBOX_BW_4CREDITS_MTL;
-		}
-
-		intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), pipe_val);
-	}
-}
-
 static int skl_watermark_ipc_status_show(struct seq_file *m, void *data)
 {
 	struct drm_i915_private *i915 = m->private;