diff mbox series

[13/22] drm/i915/mst: Limit MST+DSC to TGL+

Message ID 20240329011254.24160-14-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: Bigjoiner modeset sequence redesign and MST support | expand

Commit Message

Ville Syrjälä March 29, 2024, 1:12 a.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The MST code currently assumes that glk+ alerady supports MST+DSC,
which is incorrect. We need to check for TGL+ actually. ICL does
support SST+DSC, but supposedly it can't do MST+FEC which will
also rule MST+DSC.

Note that a straight TGL+ check doesn't work here because DSC
support can get fused out, so we do need to also check 'has_dsc'.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c         | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

Comments

Shankar, Uma April 1, 2024, 9:44 a.m. UTC | #1 
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Friday, March 29, 2024 6:43 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 13/22] drm/i915/mst: Limit MST+DSC to TGL+
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The MST code currently assumes that glk+ alerady supports MST+DSC, which is

Nit: Typo in already 

> incorrect. We need to check for TGL+ actually. ICL does support SST+DSC, but
> supposedly it can't do MST+FEC which will also rule MST+DSC.
> 
> Note that a straight TGL+ check doesn't work here because DSC support can get
> fused out, so we do need to also check 'has_dsc'.

Yeah right.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
>  drivers/gpu/drm/i915/display/intel_dp_mst.c         | 2 +-
>  2 files changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
> b/drivers/gpu/drm/i915/display/intel_display_device.h
> index fe4268813786..9b1bce2624b9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -47,6 +47,7 @@ struct drm_printer;
>  #define HAS_DPT(i915)			(DISPLAY_VER(i915) >= 13)
>  #define HAS_DSB(i915)			(DISPLAY_INFO(i915)->has_dsb)
>  #define HAS_DSC(__i915)
> 	(DISPLAY_RUNTIME_INFO(__i915)->has_dsc)
> +#define HAS_DSC_MST(__i915)		(DISPLAY_VER(__i915) >= 12 &&
> HAS_DSC(__i915))
>  #define HAS_FBC(i915)			(DISPLAY_RUNTIME_INFO(i915)-
> >fbc_mask != 0)
>  #define HAS_FPGA_DBG_UNCLAIMED(i915)	(DISPLAY_INFO(i915)-
> >has_fpga_dbg)
>  #define HAS_FW_BLC(i915)		(DISPLAY_VER(i915) >= 3)
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index a3b0026adb2d..de364ed77c08 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -1352,7 +1352,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector
> *connector,
>  		return 0;
>  	}
> 
> -	if (DISPLAY_VER(dev_priv) >= 10 &&
> +	if (HAS_DSC_MST(dev_priv) &&
>  	    drm_dp_sink_supports_dsc(intel_connector->dp.dsc_dpcd)) {
>  		/*
>  		 * TBD pass the connector BPC,
> --
> 2.43.2
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index fe4268813786..9b1bce2624b9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -47,6 +47,7 @@  struct drm_printer;
 #define HAS_DPT(i915)			(DISPLAY_VER(i915) >= 13)
 #define HAS_DSB(i915)			(DISPLAY_INFO(i915)->has_dsb)
 #define HAS_DSC(__i915)			(DISPLAY_RUNTIME_INFO(__i915)->has_dsc)
+#define HAS_DSC_MST(__i915)		(DISPLAY_VER(__i915) >= 12 && HAS_DSC(__i915))
 #define HAS_FBC(i915)			(DISPLAY_RUNTIME_INFO(i915)->fbc_mask != 0)
 #define HAS_FPGA_DBG_UNCLAIMED(i915)	(DISPLAY_INFO(i915)->has_fpga_dbg)
 #define HAS_FW_BLC(i915)		(DISPLAY_VER(i915) >= 3)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index a3b0026adb2d..de364ed77c08 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1352,7 +1352,7 @@  intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
 		return 0;
 	}
 
-	if (DISPLAY_VER(dev_priv) >= 10 &&
+	if (HAS_DSC_MST(dev_priv) &&
 	    drm_dp_sink_supports_dsc(intel_connector->dp.dsc_dpcd)) {
 		/*
 		 * TBD pass the connector BPC,