| Message ID | 20240329011254.24160-4-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Bigjoiner modeset sequence redesign and MST support | expand |
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville > Syrjala > Sent: Friday, March 29, 2024 6:43 AM > To: intel-gfx@lists.freedesktop.org > Subject: [PATCH 03/22] drm/i915: Disable live M/N updates when using > bigjoiner > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > All joined pipes share the same transcoder/timing generator. > Currently we just do the commits per-pipe, which doesn't really work if we need > to change the timings at the same time. For now just disable live M/N updates > when bigjoiner is needed. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Thanks and Regards, Arun R Murthy -------------------- > --- > drivers/gpu/drm/i915/display/intel_dp.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index f755fd974da2..bc9d6efc99ee 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -2719,7 +2719,11 @@ intel_dp_drrs_compute_config(struct > intel_connector *connector, > intel_panel_downclock_mode(connector, &pipe_config- > >hw.adjusted_mode); > int pixel_clock; > > - if (has_seamless_m_n(connector)) > + /* > + * FIXME all joined pipes share the same transcoder. > + * Need to account for that when updating M/N live. > + */ > + if (has_seamless_m_n(connector) && !pipe_config->bigjoiner_pipes) > pipe_config->update_m_n = true; > > if (!can_enable_drrs(connector, pipe_config, downclock_mode)) { > -- > 2.43.2
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index f755fd974da2..bc9d6efc99ee 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2719,7 +2719,11 @@ intel_dp_drrs_compute_config(struct intel_connector *connector, intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode); int pixel_clock; - if (has_seamless_m_n(connector)) + /* + * FIXME all joined pipes share the same transcoder. + * Need to account for that when updating M/N live. + */ + if (has_seamless_m_n(connector) && !pipe_config->bigjoiner_pipes) pipe_config->update_m_n = true; if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {