From patchwork Wed Apr 3 10:51:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Vivekanandan, Balasubramani" X-Patchwork-Id: 13615840 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 704DECD129C for ; Wed, 3 Apr 2024 10:51:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8341811263F; Wed, 3 Apr 2024 10:51:48 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="cfN+mvI/"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id A4CE011263D; Wed, 3 Apr 2024 10:51:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712141507; x=1743677507; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xzrFbXEDQUB8nd70SidKMIXoBJZQIcCHF292AjuMF8Q=; b=cfN+mvI/5kkqeWpCsAsgytZZK3h6QfgWa1B4yI0xxtHCFXN7ewC77tix bQVhAv+64Xv4Ikbp08r0uC9LtTvCqXt+jLV7c4Pej+6NAwLvOCrBDeHPu rlhlBJUSi5BRPjoIpY9UjvRypm7ei3q6u45de943VrjnQX5wkAAEhyxBc VgiMzetb1lmpxEaSKIxfjgdoyw/0PoSTVv44MShzuWF62oNKK0gEYyDql 8VULiGhdxGRfTk1az3u0vCcx0sfBwVvbMwyjIBmVHDVO3+5gKRagoqvrW 3821foDzdZg8PGKbwDI0xJp9ak8dm17W4fM1mb7cOC56jYG9ERx7aHLyK Q==; X-CSE-ConnectionGUID: M7q/0HqEQkmJFZO0W7onww== X-CSE-MsgGUID: zX7xicvWQR6o+1NTVMJcUw== X-IronPort-AV: E=McAfee;i="6600,9927,11032"; a="7212114" X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="7212114" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 03:51:18 -0700 X-CSE-ConnectionGUID: ertfrIC3SyS/BSzoz1uaKg== X-CSE-MsgGUID: 285I7zt7S3OrRuHgV+0A0A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,177,1708416000"; d="scan'208";a="18493332" Received: from bvivekan-desk.iind.intel.com ([10.190.238.63]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2024 03:51:16 -0700 From: Balasubramani Vivekanandan To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: Matt Roper , Lucas De Marchi , Balasubramani Vivekanandan Subject: [PATCH 03/25] drm/xe/bmg: Define IS_BATTLEMAGE macro Date: Wed, 3 Apr 2024 16:21:01 +0530 Message-Id: <20240403105123.1327669-4-balasubramani.vivekanandan@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240403105123.1327669-1-balasubramani.vivekanandan@intel.com> References: <20240403105123.1327669-1-balasubramani.vivekanandan@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Common display code requires IS_BATTLEMAGE macro. Defined the macro. Signed-off-by: Balasubramani Vivekanandan --- drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h index a01d1b869c2d..9161d1fdf239 100644 --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h @@ -88,6 +88,7 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) #define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, XE_DG2) #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE) #define IS_LUNARLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_LUNARLAKE) +#define IS_BATTLEMAGE(dev_priv) IS_PLATFORM(dev_priv, XE_BATTLEMAGE) #define IS_HASWELL_ULT(dev_priv) (dev_priv && 0) #define IS_BROADWELL_ULT(dev_priv) (dev_priv && 0)