| Message ID | 20240404114147.236316-5-luciano.coelho@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/display: DMC wakelock implementation | expand |
> -----Original Message----- > From: Coelho, Luciano <luciano.coelho@intel.com> > Sent: Thursday, April 4, 2024 5:12 PM > To: intel-gfx@lists.freedesktop.org > Cc: intel-xe@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>; > ville.syrjala@linux.intel.com; Nikula, Jani <jani.nikula@intel.com> > Subject: [PATCH v4 4/4] drm/i915/display: tie DMC wakelock to DC5/6 state > transitions > > We only need DMC wakelocks when we allow DC5 and DC6 states. Add the calls > to enable and disable DMC wakelock accordingly. Looks Good to me. Reviewed-by: Uma Shankar <uma.shankar@intel.com> > Signed-off-by: Luca Coelho <luciano.coelho@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display_power_well.c | 7 +++++++ > drivers/gpu/drm/i915/display/intel_dmc.c | 4 ++++ > 2 files changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c > b/drivers/gpu/drm/i915/display/intel_display_power_well.c > index e4de40228997..7f4b7602cf02 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c > @@ -17,6 +17,7 @@ > #include "intel_dkl_phy.h" > #include "intel_dkl_phy_regs.h" > #include "intel_dmc.h" > +#include "intel_dmc_wl.h" > #include "intel_dp_aux_regs.h" > #include "intel_dpio_phy.h" > #include "intel_dpll.h" > @@ -821,6 +822,8 @@ void gen9_enable_dc5(struct drm_i915_private > *dev_priv) > intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, > 0, SKL_SELECT_ALTERNATE_DC_EXIT); > > + intel_dmc_wl_enable(dev_priv); > + > gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); } > > @@ -850,6 +853,8 @@ void skl_enable_dc6(struct drm_i915_private *dev_priv) > intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, > 0, SKL_SELECT_ALTERNATE_DC_EXIT); > > + intel_dmc_wl_enable(dev_priv); > + > gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); } > > @@ -970,6 +975,8 @@ void gen9_disable_dc_states(struct drm_i915_private > *dev_priv) > if (!HAS_DISPLAY(dev_priv)) > return; > > + intel_dmc_wl_disable(dev_priv); > + > intel_cdclk_get_cdclk(dev_priv, &cdclk_config); > /* Can't read out voltage_level so can't use intel_cdclk_changed() */ > drm_WARN_ON(&dev_priv->drm, > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c > b/drivers/gpu/drm/i915/display/intel_dmc.c > index 3fa851b5c7a6..b20cc018b9a8 100644 > --- a/drivers/gpu/drm/i915/display/intel_dmc.c > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c > @@ -550,6 +550,8 @@ void intel_dmc_disable_program(struct > drm_i915_private *i915) > pipedmc_clock_gating_wa(i915, true); > disable_all_event_handlers(i915); > pipedmc_clock_gating_wa(i915, false); > + > + intel_dmc_wl_disable(i915); > } > > void assert_dmc_loaded(struct drm_i915_private *i915) @@ -1079,6 +1081,8 > @@ void intel_dmc_suspend(struct drm_i915_private *i915) > if (dmc) > flush_work(&dmc->work); > > + intel_dmc_wl_disable(i915); > + > /* Drop the reference held in case DMC isn't loaded. */ > if (!intel_dmc_has_payload(i915)) > intel_dmc_runtime_pm_put(i915); > -- > 2.39.2
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index e4de40228997..7f4b7602cf02 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -17,6 +17,7 @@ #include "intel_dkl_phy.h" #include "intel_dkl_phy_regs.h" #include "intel_dmc.h" +#include "intel_dmc_wl.h" #include "intel_dp_aux_regs.h" #include "intel_dpio_phy.h" #include "intel_dpll.h" @@ -821,6 +822,8 @@ void gen9_enable_dc5(struct drm_i915_private *dev_priv) intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0, SKL_SELECT_ALTERNATE_DC_EXIT); + intel_dmc_wl_enable(dev_priv); + gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); } @@ -850,6 +853,8 @@ void skl_enable_dc6(struct drm_i915_private *dev_priv) intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0, SKL_SELECT_ALTERNATE_DC_EXIT); + intel_dmc_wl_enable(dev_priv); + gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); } @@ -970,6 +975,8 @@ void gen9_disable_dc_states(struct drm_i915_private *dev_priv) if (!HAS_DISPLAY(dev_priv)) return; + intel_dmc_wl_disable(dev_priv); + intel_cdclk_get_cdclk(dev_priv, &cdclk_config); /* Can't read out voltage_level so can't use intel_cdclk_changed() */ drm_WARN_ON(&dev_priv->drm, diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 3fa851b5c7a6..b20cc018b9a8 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -550,6 +550,8 @@ void intel_dmc_disable_program(struct drm_i915_private *i915) pipedmc_clock_gating_wa(i915, true); disable_all_event_handlers(i915); pipedmc_clock_gating_wa(i915, false); + + intel_dmc_wl_disable(i915); } void assert_dmc_loaded(struct drm_i915_private *i915) @@ -1079,6 +1081,8 @@ void intel_dmc_suspend(struct drm_i915_private *i915) if (dmc) flush_work(&dmc->work); + intel_dmc_wl_disable(i915); + /* Drop the reference held in case DMC isn't loaded. */ if (!intel_dmc_has_payload(i915)) intel_dmc_runtime_pm_put(i915);
We only need DMC wakelocks when we allow DC5 and DC6 states. Add the calls to enable and disable DMC wakelock accordingly. Signed-off-by: Luca Coelho <luciano.coelho@intel.com> --- drivers/gpu/drm/i915/display/intel_display_power_well.c | 7 +++++++ drivers/gpu/drm/i915/display/intel_dmc.c | 4 ++++ 2 files changed, 11 insertions(+)