diff mbox series

[v2,03/11] drm/i915/dp_mst: Fix BW limit check when calculating DSC DPT bpp

Message ID 20240416221010.376865-4-imre.deak@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/dp: Few MTL/DSC and a UHBR monitor fix | expand

Commit Message

Imre Deak April 16, 2024, 10:10 p.m. UTC 
The DSC DPT bpp limit check should only fail if the available DPT BW is
less than the required BW, fix the check accordingly.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 196eeead8cf02..58eb6bf33c92e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -60,7 +60,7 @@  static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp
 		int output_bpp = bpp;
 		int symbol_clock = intel_dp_link_symbol_clock(crtc_state->port_clock);
 
-		if (output_bpp * adjusted_mode->crtc_clock >=
+		if (output_bpp * adjusted_mode->crtc_clock >
 		    symbol_clock * 72) {
 			drm_dbg_kms(&i915->drm, "UHBR check failed(required bw %d available %d)\n",
 				    output_bpp * adjusted_mode->crtc_clock, symbol_clock * 72);