From patchwork Tue Apr 16 22:10:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13632670 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 05DFFC04FF6 for ; Tue, 16 Apr 2024 22:09:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 00EFF112EB4; Tue, 16 Apr 2024 22:09:45 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="O0IoRVlt"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9C9D1112EA9 for ; Tue, 16 Apr 2024 22:09:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713305382; x=1744841382; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BFZG4IL8coiMgG9X3CGVtmXqR0lCAL7wCbuRfWjlToU=; b=O0IoRVltgFGjxobbZmmdnRmyp4EXA9jiBDNOmPulupTIR/I11Uwxf1ID PLzc2XYVpkPkK45PYMRplyWzVh/2WP9TUqCegEAKkuhXjGAzflihDkiNY PkE3jQuvktdkRf125Gc97sGPWOHZJaufMqEwLnuT6Cj0APjOZcLVzCDk4 N6rw0QzohUHlfYhBqx8pdasGIKkJr7WS3QxZ89zsJA30qxBApES8Vvo26 DmuHFEisaFce0tAjowgEK7aZAS+0oa0/VzIaKHek8SUoCjF8YCw7u5DsU WPEJwBhEockQPFFBjKKg5Ai4qXJ1Yl1YEt0QzOnUYlyDma59h7PamPTGN A==; X-CSE-ConnectionGUID: sEx8YhPdSHCaEAUFQ7tQ2Q== X-CSE-MsgGUID: scpEJB1gQF6Ec6SjLcPQjA== X-IronPort-AV: E=McAfee;i="6600,9927,11046"; a="20165152" X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="20165152" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:41 -0700 X-CSE-ConnectionGUID: /j7zNSjxTmin1k+GCWbtOw== X-CSE-MsgGUID: XtA+oNRtSXavI/fQtxRlhA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,207,1708416000"; d="scan'208";a="26965479" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2024 15:09:41 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: Ankit Nautiyal Subject: [PATCH v2 03/11] drm/i915/dp_mst: Fix BW limit check when calculating DSC DPT bpp Date: Wed, 17 Apr 2024 01:10:02 +0300 Message-ID: <20240416221010.376865-4-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240416221010.376865-1-imre.deak@intel.com> References: <20240416221010.376865-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The DSC DPT bpp limit check should only fail if the available DPT BW is less than the required BW, fix the check accordingly. Reviewed-by: Ankit Nautiyal Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 196eeead8cf02..58eb6bf33c92e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -60,7 +60,7 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp int output_bpp = bpp; int symbol_clock = intel_dp_link_symbol_clock(crtc_state->port_clock); - if (output_bpp * adjusted_mode->crtc_clock >= + if (output_bpp * adjusted_mode->crtc_clock > symbol_clock * 72) { drm_dbg_kms(&i915->drm, "UHBR check failed(required bw %d available %d)\n", output_bpp * adjusted_mode->crtc_clock, symbol_clock * 72);