| Message ID | 20240426000723.229296-1-andi.shyti@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/gt: Automate CCS Mode setting during engine resets | expand |
Hi, On Fri, Apr 26, 2024 at 02:07:23AM +0200, Andi Shyti wrote: > We missed setting the CCS mode during resume and engine resets. > Create a workaround to be added in the engine's workaround list. > This workaround sets the XEHP_CCS_MODE value at every reset. > > The issue can be reproduced by running: > > $ clpeak --kernel-latency > > Without resetting the CCS mode, we encounter a fence timeout: > > Fence expiration time out i915-0000:03:00.0:clpeak[2387]:2! > > Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10895 > Fixes: 6db31251bb26 ("drm/i915/gt: Enable only one CCS for compute workload") > Reported-by: Gnattu OC <gnattuoc@me.com> > Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> > Cc: Chris Wilson <chris.p.wilson@linux.intel.com> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > Cc: Matt Roper <matthew.d.roper@intel.com> > Cc: <stable@vger.kernel.org> # v6.2+ based on the discussion on the issue and as agreed with Gnattu: Tested-by: Gnattu OC <gnattuoc@me.com> Thank you again, gnattu, Andi
On Fri, Apr 26, 2024 at 02:07:23AM +0200, Andi Shyti wrote: > We missed setting the CCS mode during resume and engine resets. > Create a workaround to be added in the engine's workaround list. > This workaround sets the XEHP_CCS_MODE value at every reset. > > The issue can be reproduced by running: > > $ clpeak --kernel-latency > > Without resetting the CCS mode, we encounter a fence timeout: > > Fence expiration time out i915-0000:03:00.0:clpeak[2387]:2! > > Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10895 > Fixes: 6db31251bb26 ("drm/i915/gt: Enable only one CCS for compute workload") > Reported-by: Gnattu OC <gnattuoc@me.com> > Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> > Cc: Chris Wilson <chris.p.wilson@linux.intel.com> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > Cc: Matt Roper <matthew.d.roper@intel.com> > Cc: <stable@vger.kernel.org> # v6.2+ Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > Hi Gnattu, > > thanks again for reporting this issue and for your prompt > replies on the issue. Would you give this patch a chance? > > Andi > > drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 6 +++--- > drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h | 2 +- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 +++- > 3 files changed, 7 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c > index 044219c5960a..99b71bb7da0a 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c > @@ -8,14 +8,14 @@ > #include "intel_gt_ccs_mode.h" > #include "intel_gt_regs.h" > > -void intel_gt_apply_ccs_mode(struct intel_gt *gt) > +unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt) > { > int cslice; > u32 mode = 0; > int first_ccs = __ffs(CCS_MASK(gt)); > > if (!IS_DG2(gt->i915)) > - return; > + return 0; > > /* Build the value for the fixed CCS load balancing */ > for (cslice = 0; cslice < I915_MAX_CCS; cslice++) { > @@ -35,5 +35,5 @@ void intel_gt_apply_ccs_mode(struct intel_gt *gt) > XEHP_CCS_MODE_CSLICE_MASK); > } > > - intel_uncore_write(gt->uncore, XEHP_CCS_MODE, mode); > + return mode; > } > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h > index 9e5549caeb26..55547f2ff426 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h > @@ -8,6 +8,6 @@ > > struct intel_gt; > > -void intel_gt_apply_ccs_mode(struct intel_gt *gt); > +unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt); > > #endif /* __INTEL_GT_CCS_MODE_H__ */ > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 68b6aa11bcf7..58693923bf6c 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -2703,6 +2703,7 @@ add_render_compute_tuning_settings(struct intel_gt *gt, > static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_list *wal) > { > struct intel_gt *gt = engine->gt; > + u32 mode; > > if (!IS_DG2(gt->i915)) > return; > @@ -2719,7 +2720,8 @@ static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_li > * After having disabled automatic load balancing we need to > * assign all slices to a single CCS. We will call it CCS mode 1 > */ > - intel_gt_apply_ccs_mode(gt); > + mode = intel_gt_apply_ccs_mode(gt); > + wa_masked_en(wal, XEHP_CCS_MODE, mode); > } > > /* > -- > 2.43.0 >
Tested-by: Krzysztof Gibala <krzysztof.gibala@intel.com> -----Original Message----- From: Andi Shyti <andi.shyti@linux.intel.com> Sent: Friday, April 26, 2024 2:07 AM To: intel-gfx <intel-gfx@lists.freedesktop.org>; dri-devel <dri-devel@lists.freedesktop.org> Cc: Andi Shyti <andi.shyti@linux.intel.com>; Andi Shyti <andi.shyti@kernel.org>; Gnattu OC <gnattuoc@me.com>; Chris Wilson <chris.p.wilson@linux.intel.com>; Joonas Lahtinen <joonas.lahtinen@linux.intel.com>; Roper, Matthew D <matthew.d.roper@intel.com>; stable@vger.kernel.org Subject: [PATCH] drm/i915/gt: Automate CCS Mode setting during engine resets We missed setting the CCS mode during resume and engine resets. Create a workaround to be added in the engine's workaround list. This workaround sets the XEHP_CCS_MODE value at every reset. The issue can be reproduced by running: $ clpeak --kernel-latency Without resetting the CCS mode, we encounter a fence timeout: Fence expiration time out i915-0000:03:00.0:clpeak[2387]:2! Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10895 Fixes: 6db31251bb26 ("drm/i915/gt: Enable only one CCS for compute workload") Reported-by: Gnattu OC <gnattuoc@me.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Cc: Chris Wilson <chris.p.wilson@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: <stable@vger.kernel.org> # v6.2+ --- Hi Gnattu, thanks again for reporting this issue and for your prompt replies on the issue. Would you give this patch a chance? Andi drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 6 +++--- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h | 2 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 +++- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index 044219c5960a..99b71bb7da0a 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -8,14 +8,14 @@ #include "intel_gt_ccs_mode.h" #include "intel_gt_regs.h" -void intel_gt_apply_ccs_mode(struct intel_gt *gt) +unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt) { int cslice; u32 mode = 0; int first_ccs = __ffs(CCS_MASK(gt)); if (!IS_DG2(gt->i915)) - return; + return 0; /* Build the value for the fixed CCS load balancing */ for (cslice = 0; cslice < I915_MAX_CCS; cslice++) { @@ -35,5 +35,5 @@ void intel_gt_apply_ccs_mode(struct intel_gt *gt) XEHP_CCS_MODE_CSLICE_MASK); } - intel_uncore_write(gt->uncore, XEHP_CCS_MODE, mode); + return mode; } diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h index 9e5549caeb26..55547f2ff426 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h @@ -8,6 +8,6 @@ struct intel_gt; -void intel_gt_apply_ccs_mode(struct intel_gt *gt); +unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt); #endif /* __INTEL_GT_CCS_MODE_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 68b6aa11bcf7..58693923bf6c 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2703,6 +2703,7 @@ add_render_compute_tuning_settings(struct intel_gt *gt, static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_list *wal) { struct intel_gt *gt = engine->gt; + u32 mode; if (!IS_DG2(gt->i915)) return; @@ -2719,7 +2720,8 @@ static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_li * After having disabled automatic load balancing we need to * assign all slices to a single CCS. We will call it CCS mode 1 */ - intel_gt_apply_ccs_mode(gt); + mode = intel_gt_apply_ccs_mode(gt); + wa_masked_en(wal, XEHP_CCS_MODE, mode); } /* -- 2.43.0 --------------------------------------------------------------------- Intel Technology Poland sp. z o.o. ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | Kapital zakladowy 200.000 PLN. Spolka oswiadcza, ze posiada status duzego przedsiebiorcy w rozumieniu ustawy z dnia 8 marca 2013 r. o przeciwdzialaniu nadmiernym opoznieniom w transakcjach handlowych. Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i moze zawierac informacje poufne. W razie przypadkowego otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; jakiekolwiek przegladanie lub rozpowszechnianie jest zabronione. This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). If you are not the intended recipient, please contact the sender and delete all copies; any review or distribution by others is strictly prohibited.
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index 044219c5960a..99b71bb7da0a 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -8,14 +8,14 @@ #include "intel_gt_ccs_mode.h" #include "intel_gt_regs.h" -void intel_gt_apply_ccs_mode(struct intel_gt *gt) +unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt) { int cslice; u32 mode = 0; int first_ccs = __ffs(CCS_MASK(gt)); if (!IS_DG2(gt->i915)) - return; + return 0; /* Build the value for the fixed CCS load balancing */ for (cslice = 0; cslice < I915_MAX_CCS; cslice++) { @@ -35,5 +35,5 @@ void intel_gt_apply_ccs_mode(struct intel_gt *gt) XEHP_CCS_MODE_CSLICE_MASK); } - intel_uncore_write(gt->uncore, XEHP_CCS_MODE, mode); + return mode; } diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h index 9e5549caeb26..55547f2ff426 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h @@ -8,6 +8,6 @@ struct intel_gt; -void intel_gt_apply_ccs_mode(struct intel_gt *gt); +unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt); #endif /* __INTEL_GT_CCS_MODE_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 68b6aa11bcf7..58693923bf6c 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2703,6 +2703,7 @@ add_render_compute_tuning_settings(struct intel_gt *gt, static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_list *wal) { struct intel_gt *gt = engine->gt; + u32 mode; if (!IS_DG2(gt->i915)) return; @@ -2719,7 +2720,8 @@ static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_li * After having disabled automatic load balancing we need to * assign all slices to a single CCS. We will call it CCS mode 1 */ - intel_gt_apply_ccs_mode(gt); + mode = intel_gt_apply_ccs_mode(gt); + wa_masked_en(wal, XEHP_CCS_MODE, mode); } /*
We missed setting the CCS mode during resume and engine resets. Create a workaround to be added in the engine's workaround list. This workaround sets the XEHP_CCS_MODE value at every reset. The issue can be reproduced by running: $ clpeak --kernel-latency Without resetting the CCS mode, we encounter a fence timeout: Fence expiration time out i915-0000:03:00.0:clpeak[2387]:2! Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10895 Fixes: 6db31251bb26 ("drm/i915/gt: Enable only one CCS for compute workload") Reported-by: Gnattu OC <gnattuoc@me.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Cc: Chris Wilson <chris.p.wilson@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: <stable@vger.kernel.org> # v6.2+ --- Hi Gnattu, thanks again for reporting this issue and for your prompt replies on the issue. Would you give this patch a chance? Andi drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 6 +++--- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h | 2 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 +++- 3 files changed, 7 insertions(+), 5 deletions(-)