| Message ID | 20240503060621.987820-3-jouni.hogander@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | LunarLake IO and Fast Wake changes | expand |
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jouni > Högander > Sent: Friday, May 3, 2024 11:36 AM > To: intel-gfx@lists.freedesktop.org > Cc: Hogander, Jouni <jouni.hogander@intel.com> > Subject: [PATCH 2/3] drm/i915/psr: LunarLake PSR2_CTL[IO Wake Lines] is 6 bits > wide > > On LunarLake PSR2_CTL[IO Wake Lines] contains now bit 13:18. Take this into > account when enabling PSR2_CTL. Looks Good to me. Reviewed-by: Uma Shankar <uma.shankar@intel.com> > Bspec: 69885 > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 2 ++ > drivers/gpu/drm/i915/display/intel_psr_regs.h | 4 ++++ > 2 files changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index 678987bbe168..4d67a384e149 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -900,6 +900,8 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) > > tmp = map[psr->alpm_parameters.fast_wake_lines - > TGL_EDP_PSR2_FAST_WAKE_MIN_LINES]; > val |= TGL_EDP_PSR2_FAST_WAKE(tmp + > TGL_EDP_PSR2_FAST_WAKE_MIN_LINES); > + } else if (DISPLAY_VER(dev_priv) >= 20) { > + val |= > +LNL_EDP_PSR2_IO_BUFFER_WAKE(psr->alpm_parameters.io_wake_lines); > } else if (DISPLAY_VER(dev_priv) >= 12) { > val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(psr- > >alpm_parameters.io_wake_lines); > val |= TGL_EDP_PSR2_FAST_WAKE(psr- > >alpm_parameters.fast_wake_lines); > diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h > b/drivers/gpu/drm/i915/display/intel_psr_regs.h > index ebc22999572c..68381bbf462e 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h > @@ -172,6 +172,10 @@ > #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5 > #define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) > REG_FIELD_PREP(TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK, \ > (lines) - > TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) > +#define LNL_EDP_PSR2_IO_BUFFER_WAKE_MASK REG_GENMASK(18, 13) > +#define LNL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5 > +#define LNL_EDP_PSR2_IO_BUFFER_WAKE(lines) > REG_FIELD_PREP(LNL_EDP_PSR2_IO_BUFFER_WAKE_MASK, \ > + (lines) - > LNL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) > #define EDP_PSR2_FAST_WAKE_MASK REG_GENMASK(12, 11) > #define EDP_PSR2_FAST_WAKE_MAX_LINES 8 > #define EDP_PSR2_FAST_WAKE(lines) > REG_FIELD_PREP(EDP_PSR2_FAST_WAKE_MASK, \ > -- > 2.34.1
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 678987bbe168..4d67a384e149 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -900,6 +900,8 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) tmp = map[psr->alpm_parameters.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES]; val |= TGL_EDP_PSR2_FAST_WAKE(tmp + TGL_EDP_PSR2_FAST_WAKE_MIN_LINES); + } else if (DISPLAY_VER(dev_priv) >= 20) { + val |= LNL_EDP_PSR2_IO_BUFFER_WAKE(psr->alpm_parameters.io_wake_lines); } else if (DISPLAY_VER(dev_priv) >= 12) { val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(psr->alpm_parameters.io_wake_lines); val |= TGL_EDP_PSR2_FAST_WAKE(psr->alpm_parameters.fast_wake_lines); diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index ebc22999572c..68381bbf462e 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -172,6 +172,10 @@ #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5 #define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) REG_FIELD_PREP(TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK, \ (lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) +#define LNL_EDP_PSR2_IO_BUFFER_WAKE_MASK REG_GENMASK(18, 13) +#define LNL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5 +#define LNL_EDP_PSR2_IO_BUFFER_WAKE(lines) REG_FIELD_PREP(LNL_EDP_PSR2_IO_BUFFER_WAKE_MASK, \ + (lines) - LNL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) #define EDP_PSR2_FAST_WAKE_MASK REG_GENMASK(12, 11) #define EDP_PSR2_FAST_WAKE_MAX_LINES 8 #define EDP_PSR2_FAST_WAKE(lines) REG_FIELD_PREP(EDP_PSR2_FAST_WAKE_MASK, \
On LunarLake PSR2_CTL[IO Wake Lines] contains now bit 13:18. Take this into account when enabling PSR2_CTL. Bspec: 69885 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 2 ++ drivers/gpu/drm/i915/display/intel_psr_regs.h | 4 ++++ 2 files changed, 6 insertions(+)