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[91.156.196.125]) by smtp.gmail.com with ESMTPSA id c11-20020a05651c014b00b002dcdeb98653sm1673945ljd.8.2024.05.06.11.52.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 May 2024 11:52:49 -0700 (PDT) From: Juha-Pekka Heikkila To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Cc: Juha-Pekka Heikkila , "Chery, Nanley G" , "Saarinen, Jani" , "Graunke, Kenneth W" , "Souza, Jose" , "Mathew, Alwin" , "Zhang, Jianxun" , "Syrjala, Ville" , "Nikula, Jani" Subject: [RFC PATCH 1/3] drm/fourcc: define Intel Xe2 related tile4 ccs modifier Date: Mon, 6 May 2024 21:52:36 +0300 Message-Id: <20240506185238.364539-2-juhapekka.heikkila@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240506185238.364539-1-juhapekka.heikkila@gmail.com> References: <20240506185238.364539-1-juhapekka.heikkila@gmail.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add Tile4 type ccs modifier to indicate presence of compression on Xe2 Signed-off-by: Juha-Pekka Heikkila --- include/uapi/drm/drm_fourcc.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 84d502e42961..50db2cc89642 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -702,6 +702,18 @@ extern "C" { */ #define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15) +/* + * Intel Color Control Surfaces (CCS) for graphics ver. 20 render compression. + * + * The main surface is Tile 4 and at plane index 0. For semi-planar formats + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices + * 0 and 1, respectively. The CCS for all planes are stored outside of the + * GEM object in a reserved memory area dedicated for the storage of the + * CCS data for all compressible GEM objects. The main surface pitch is + * required to be a multiple of four Tile 4 widths. + */ +#define I915_FORMAT_MOD_4_TILED_XE2_CCS fourcc_mod_code(INTEL, 16) + /* * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks *