| Message ID | 20240514133143.718389-1-animesh.manna@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v5] drm/i915/panelreplay: Panel replay workaround with VRR | expand |
Hi @Animesh Manna > -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of > Animesh Manna > Sent: Tuesday, May 14, 2024 7:02 PM > To: intel-gfx@lists.freedesktop.org > Cc: Nikula, Jani <jani.nikula@intel.com>; ville.syrjala@linux.intel.com; > Hogander, Jouni <jouni.hogander@intel.com>; Murthy, Arun R > <arun.r.murthy@intel.com>; Manna, Animesh <animesh.manna@intel.com> > Subject: [PATCH v5] drm/i915/panelreplay: Panel replay workaround with > VRR > > Panel Replay VSC SDP not getting sent when VRR is enabled and W1 and W2 > are 0. So Program Set Context Latency in TRANS_SET_CONTEXT_LATENCY > register to at least a value of 1. > > HSD: 14015406119 > > v1: Initial version. > v2: Update timings stored in adjusted_mode struct. [Ville] > v3: Add WA in compute_config(). [Ville] > v4: > - Add DISPLAY_VER() check and improve code comment. [Rodrigo] > - Introduce centralized intel_crtc_vblank_delay(). [Ville] > v5: Move to crtc_compute_config(). [Ville] > > Signed-off-by: Animesh Manna <animesh.manna@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 22 ++++++++++++++++++++ > drivers/gpu/drm/i915/display/intel_display.h | 1 + > 2 files changed, 23 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index ef986b508431..0664c9478c68 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -2497,10 +2497,15 @@ static int intel_crtc_compute_pipe_mode(struct > intel_crtc_state *crtc_state) static int intel_crtc_compute_config(struct > intel_atomic_state *state, > struct intel_crtc *crtc) > { > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > struct intel_crtc_state *crtc_state = > intel_atomic_get_new_crtc_state(state, crtc); > int ret; > > + /* wa_14015401596: display versions 13, 14 */ > + if (DISPLAY_VER(dev_priv) >= 13) > + intel_crtc_vblank_delay(crtc_state); > + Perhaps to restrict till DISPLAY_VER 14 as mentioned in comment? Please confirm once with WA details ? Regards, Mitul > ret = intel_dpll_crtc_compute_clock(state, crtc); > if (ret) > return ret; > @@ -3889,6 +3894,23 @@ bool intel_crtc_get_pipe_config(struct > intel_crtc_state *crtc_state) > return true; > } > > +void intel_crtc_vblank_delay(struct intel_crtc_state *crtc_state) { > + struct drm_display_mode *adjusted_mode = > +&crtc_state->hw.adjusted_mode; > + > + /* > + * wa_14015401596 for display versions >= 13. > + * Program Set Context Latency in TRANS_SET_CONTEXT_LATENCY > register > + * to at least a value of 1 when Panel Replay is enabled with VRR. > + * Value for TRANS_SET_CONTEXT_LATENCY is calculated by > substracting > + * crtc_vdisplay from crtc_vblank_start, so incrementing > crtc_vblank_start > + * by 1 if both are equal. > + */ > + if (crtc_state->vrr.enable && crtc_state->has_panel_replay && > + adjusted_mode->crtc_vblank_start == adjusted_mode- > >crtc_vdisplay) > + adjusted_mode->crtc_vblank_start += 1; } > + > int intel_dotclock_calculate(int link_freq, > const struct intel_link_m_n *m_n) { diff --git > a/drivers/gpu/drm/i915/display/intel_display.h > b/drivers/gpu/drm/i915/display/intel_display.h > index 56d1c0e3e62c..d426dd9f7f87 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.h > +++ b/drivers/gpu/drm/i915/display/intel_display.h > @@ -428,6 +428,7 @@ bool intel_crtc_is_bigjoiner_master(const struct > intel_crtc_state *crtc_state); > u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state); > struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state); > bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state); > +void intel_crtc_vblank_delay(struct intel_crtc_state *crtc_state); > bool intel_pipe_config_compare(const struct intel_crtc_state > *current_config, > const struct intel_crtc_state *pipe_config, > bool fastset); > -- > 2.29.0
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ef986b508431..0664c9478c68 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2497,10 +2497,15 @@ static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) static int intel_crtc_compute_config(struct intel_atomic_state *state, struct intel_crtc *crtc) { + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); int ret; + /* wa_14015401596: display versions 13, 14 */ + if (DISPLAY_VER(dev_priv) >= 13) + intel_crtc_vblank_delay(crtc_state); + ret = intel_dpll_crtc_compute_clock(state, crtc); if (ret) return ret; @@ -3889,6 +3894,23 @@ bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state) return true; } +void intel_crtc_vblank_delay(struct intel_crtc_state *crtc_state) +{ + struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + + /* + * wa_14015401596 for display versions >= 13. + * Program Set Context Latency in TRANS_SET_CONTEXT_LATENCY register + * to at least a value of 1 when Panel Replay is enabled with VRR. + * Value for TRANS_SET_CONTEXT_LATENCY is calculated by substracting + * crtc_vdisplay from crtc_vblank_start, so incrementing crtc_vblank_start + * by 1 if both are equal. + */ + if (crtc_state->vrr.enable && crtc_state->has_panel_replay && + adjusted_mode->crtc_vblank_start == adjusted_mode->crtc_vdisplay) + adjusted_mode->crtc_vblank_start += 1; +} + int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n) { diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 56d1c0e3e62c..d426dd9f7f87 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -428,6 +428,7 @@ bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state); u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state); struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state); bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state); +void intel_crtc_vblank_delay(struct intel_crtc_state *crtc_state); bool intel_pipe_config_compare(const struct intel_crtc_state *current_config, const struct intel_crtc_state *pipe_config, bool fastset);
Panel Replay VSC SDP not getting sent when VRR is enabled and W1 and W2 are 0. So Program Set Context Latency in TRANS_SET_CONTEXT_LATENCY register to at least a value of 1. HSD: 14015406119 v1: Initial version. v2: Update timings stored in adjusted_mode struct. [Ville] v3: Add WA in compute_config(). [Ville] v4: - Add DISPLAY_VER() check and improve code comment. [Rodrigo] - Introduce centralized intel_crtc_vblank_delay(). [Ville] v5: Move to crtc_compute_config(). [Ville] Signed-off-by: Animesh Manna <animesh.manna@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 22 ++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_display.h | 1 + 2 files changed, 23 insertions(+)