From patchwork Thu May 16 08:49:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 13665885 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 61845C25B7A for ; Thu, 16 May 2024 08:50:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 965A510EC39; Thu, 16 May 2024 08:50:36 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="RwjcDzfb"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2318210EC32 for ; Thu, 16 May 2024 08:50:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1715849433; x=1747385433; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gFev6wP1TvgBvah4GX4ut9iQMW9XlwcC/j0QRJNiEGU=; b=RwjcDzfbNq5ibpGp+aY4hYjJTquxItsHg/OWQtplY0eXnXzLcwSkwbWU ePuieQWG7DJ0sRIE/vEV6WR2C7KlIspPJ1K4vjlMLiJSliYL7I7BhdZrm GUtkkUpSUwuY2xbOm8GiSXtcB0PpSmSn6LhjpPOLN6U5cvaegPeeipysh eYWE1+es4jWG2xkAhBUY+DL6cYH1Y6M2Mil0SpcM3Mc/xl4+xnk6PCXD0 cOIPkGsp5GnVC5QMQFJtnpNvUWw4LJheLm7KP7SPer97nZtPsdxIhIc8a mAK16Yb4iZ+iGs419g8V3QMaVVGtf7MYQBn4g1EA4is1uqEHN+nJct9Wi w==; X-CSE-ConnectionGUID: RXCejf9hTN6zvkuU8Pe/5A== X-CSE-MsgGUID: 4Ixpx2dRTjmlrFL5+7rZeA== X-IronPort-AV: E=McAfee;i="6600,9927,11074"; a="11756098" X-IronPort-AV: E=Sophos;i="6.08,164,1712646000"; d="scan'208";a="11756098" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 May 2024 01:50:33 -0700 X-CSE-ConnectionGUID: Xka/OMkvRVa1SQhc4HfMAQ== X-CSE-MsgGUID: dYINQWVdTU2KSPG933CHpQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,164,1712646000"; d="scan'208";a="31398226" Received: from tlonnber-mobl3.ger.corp.intel.com (HELO jhogande-mobl1.intel.com) ([10.251.211.12]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 May 2024 01:50:31 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Cc: animesh.manna@intel.com, =?utf-8?q?Jouni_H=C3=B6gander?= Subject: [PATCH 15/17] drm/i915/psr: Modify dg2_activate_panel_replay to support eDP Date: Thu, 16 May 2024 11:49:55 +0300 Message-Id: <20240516084957.1557028-16-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240516084957.1557028-1-jouni.hogander@intel.com> References: <20240516084957.1557028-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" There are couple of bits in PSR2_CTL which needs to be written in case of eDP Panel Replay Bspec: 68920 Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index a84a7208e148..647e5cd70cc8 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -928,6 +928,18 @@ static u8 frames_before_su_entry(struct intel_dp *intel_dp) static void dg2_activate_panel_replay(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + struct intel_psr *psr = &intel_dp->psr; + enum transcoder cpu_transcoder = intel_dp->psr.transcoder; + + if (intel_dp_is_edp(intel_dp) && psr->sel_update_enabled) { + u32 val = LNL_EDP_PSR2_SU_REGION_ET_ENABLE; + + if (intel_dp->psr.req_psr2_sdp_prior_scanline) + val |= EDP_PSR2_SU_SDP_SCANLINE; + + intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv, cpu_transcoder), + val); + } intel_de_rmw(dev_priv, PSR2_MAN_TRK_CTL(dev_priv, intel_dp->psr.transcoder),