From patchwork Mon May 20 07:38:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanislav Lisovskiy X-Patchwork-Id: 13668090 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 10694C25B78 for ; Mon, 20 May 2024 07:38:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4F9A810E2EC; Mon, 20 May 2024 07:38:53 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="BNKW1jz8"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id BDF5310E10E for ; Mon, 20 May 2024 07:38:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716190730; x=1747726730; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eXRPd5uKWeHbA97w1Pgklqb5hu9PZc+Ok6QjMA8E0X8=; b=BNKW1jz8ebAQsJHrBUcOsQqZAOOEOS00pGpcPWaNBT4pl6/nc2RNZFX/ nrttJheNrgHjJMR7WiV8nsFOJb33QoE2EKacPbIKXBxhbQQU01Wt1ZXkO zXe/0as75nLCFSQIYwLX4BlW+93FVxn9r9WA9bHeFPC1TllX8ecYTd+Wg LAR+QkvjgXtIPxnQGrbNr2FQhqoICSK7YxPFprZvR1fO/4kW0Ux1+3U9Z Icuf4T+WBLtR3o2tcqn9CnLeKMyYw9NLz+yKZbBa3ufljRS2Rx9VkqE+a E2651rzh3V+D6Aqj++BL4oP93zUzY/3N9xwucwo2hbzRalOu9Vm6YDttS w==; X-CSE-ConnectionGUID: OfugzXNSR823zgRwG1j9NQ== X-CSE-MsgGUID: y3icNyZDTsqHpgqK411g8A== X-IronPort-AV: E=McAfee;i="6600,9927,11077"; a="23445005" X-IronPort-AV: E=Sophos;i="6.08,174,1712646000"; d="scan'208";a="23445005" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 00:38:50 -0700 X-CSE-ConnectionGUID: eA61C1pmTzqtZggkPsiwWA== X-CSE-MsgGUID: H7PQNmWAQP2hS4urrGU0HQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,174,1712646000"; d="scan'208";a="33053230" Received: from unknown (HELO slisovsk-Lenovo-ideapad-720S-13IKB.fi.intel.com) ([10.237.72.65]) by orviesa007.jf.intel.com with ESMTP; 20 May 2024 00:38:48 -0700 From: Stanislav Lisovskiy To: intel-gfx@lists.freedesktop.org Cc: jani.saarinen@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 5/5] drm/i915: Add new abstraction layer to handle pipe order for different joiners Date: Mon, 20 May 2024 10:38:39 +0300 Message-Id: <20240520073839.23881-6-stanislav.lisovskiy@intel.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20240520073839.23881-1-stanislav.lisovskiy@intel.com> References: <20240520073839.23881-1-stanislav.lisovskiy@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Ultrajoiner case requires special treatment where both reverse and staight order iteration doesn't work(for instance disabling case requires order to be: primary master, slaves, secondary master). Lets unify our approach by using not only pipe masks for iterating required pipes based on joiner type used, but also using different "priority" arrays for each of those. Signed-off-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/display/intel_ddi.c | 19 ++--- drivers/gpu/drm/i915/display/intel_display.c | 73 +++++++++++++++----- drivers/gpu/drm/i915/display/intel_display.h | 7 ++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 19 ++--- 4 files changed, 86 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 81f644533504..6cd0c545b85f 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3102,10 +3102,11 @@ static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, const struct drm_connector_state *old_conn_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - struct intel_crtc *pipe_crtc; + struct intel_crtc *pipe_crtc; enum pipe pipe; - for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc, - intel_crtc_joined_pipe_mask(old_crtc_state)) { + for_each_intel_crtc_in_mask_priority(dev_priv, pipe_crtc, pipe, + intel_crtc_joined_pipe_mask(old_crtc_state), + intel_get_pipe_order_disable(old_crtc_state)) { const struct intel_crtc_state *old_pipe_crtc_state = intel_atomic_get_old_crtc_state(state, pipe_crtc); @@ -3116,8 +3117,9 @@ static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, intel_ddi_disable_transcoder_func(old_crtc_state); - for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc, - intel_crtc_joined_pipe_mask(old_crtc_state)) { + for_each_intel_crtc_in_mask_priority(dev_priv, pipe_crtc, pipe, + intel_crtc_joined_pipe_mask(old_crtc_state), + intel_get_pipe_order_disable(old_crtc_state)) { const struct intel_crtc_state *old_pipe_crtc_state = intel_atomic_get_old_crtc_state(state, pipe_crtc); @@ -3369,7 +3371,7 @@ static void intel_enable_ddi(struct intel_atomic_state *state, const struct drm_connector_state *conn_state) { struct drm_i915_private *i915 = to_i915(encoder->base.dev); - struct intel_crtc *pipe_crtc; + struct intel_crtc *pipe_crtc; enum pipe pipe; intel_ddi_enable_transcoder_func(encoder, crtc_state); @@ -3380,8 +3382,9 @@ static void intel_enable_ddi(struct intel_atomic_state *state, intel_ddi_wait_for_fec_status(encoder, crtc_state, true); - for_each_intel_crtc_in_pipe_mask_reverse(&i915->drm, pipe_crtc, - intel_crtc_joined_pipe_mask(crtc_state)) { + for_each_intel_crtc_in_mask_priority(i915, pipe_crtc, pipe, + intel_crtc_joined_pipe_mask(crtc_state), + intel_get_pipe_order_enable(crtc_state)) { const struct intel_crtc_state *pipe_crtc_state = intel_atomic_get_new_crtc_state(state, pipe_crtc); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 6510476ac98c..7e62604c1e12 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1696,6 +1696,40 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta hsw_set_transconf(crtc_state); } + + +const enum pipe *intel_get_pipe_order_enable(const struct intel_crtc_state *crtc_state) +{ + static const enum pipe ultrajoiner_pipe_order_enable[I915_MAX_PIPES] = + { PIPE_B, PIPE_D, PIPE_C, PIPE_A }; + static const enum pipe bigjoiner_pipe_order_enable[I915_MAX_PIPES] = + { PIPE_B, PIPE_A, PIPE_D, PIPE_C }; + static const enum pipe nojoiner_pipe_order_enable[I915_MAX_PIPES] = + { PIPE_A, PIPE_B, PIPE_C, PIPE_D }; + + if (intel_is_ultrajoiner(crtc_state)) + return ultrajoiner_pipe_order_enable; + else if (intel_is_bigjoiner(crtc_state)) + return bigjoiner_pipe_order_enable; + return nojoiner_pipe_order_enable; +} + +const enum pipe *intel_get_pipe_order_disable(const struct intel_crtc_state *crtc_state) +{ + static const enum pipe ultrajoiner_pipe_order_disable[I915_MAX_PIPES] = + { PIPE_A, PIPE_B, PIPE_D, PIPE_C }; + static const enum pipe bigjoiner_pipe_order_disable[I915_MAX_PIPES] = + { PIPE_A, PIPE_B, PIPE_C, PIPE_D }; + static const enum pipe nojoiner_pipe_order_disable[I915_MAX_PIPES] = + { PIPE_A, PIPE_B, PIPE_C, PIPE_D }; + + if (intel_is_ultrajoiner(crtc_state)) + return ultrajoiner_pipe_order_disable; + else if (intel_is_bigjoiner(crtc_state)) + return bigjoiner_pipe_order_disable; + return nojoiner_pipe_order_disable; +} + static void hsw_crtc_enable(struct intel_atomic_state *state, struct intel_crtc *crtc) { @@ -1703,19 +1737,21 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; - struct intel_crtc *pipe_crtc; + struct intel_crtc *pipe_crtc; enum pipe pipe; if (drm_WARN_ON(&dev_priv->drm, crtc->active)) return; - for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc, - intel_crtc_joined_pipe_mask(new_crtc_state)) + for_each_intel_crtc_in_mask_priority(dev_priv, pipe_crtc, pipe, + intel_crtc_joined_pipe_mask(new_crtc_state), + intel_get_pipe_order_enable(new_crtc_state)) intel_dmc_enable_pipe(dev_priv, pipe_crtc->pipe); intel_encoders_pre_pll_enable(state, crtc); - for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc, - intel_crtc_joined_pipe_mask(new_crtc_state)) { + for_each_intel_crtc_in_mask_priority(dev_priv, pipe_crtc, pipe, + intel_crtc_joined_pipe_mask(new_crtc_state), + intel_get_pipe_order_enable(new_crtc_state)) { const struct intel_crtc_state *pipe_crtc_state = intel_atomic_get_new_crtc_state(state, pipe_crtc); @@ -1725,8 +1761,9 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, intel_encoders_pre_enable(state, crtc); - for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc, - intel_crtc_joined_pipe_mask(new_crtc_state)) { + for_each_intel_crtc_in_mask_priority(dev_priv, pipe_crtc, pipe, + intel_crtc_joined_pipe_mask(new_crtc_state), + intel_get_pipe_order_enable(new_crtc_state)) { const struct intel_crtc_state *pipe_crtc_state = intel_atomic_get_new_crtc_state(state, pipe_crtc); @@ -1744,8 +1781,9 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, if (!transcoder_is_dsi(cpu_transcoder)) hsw_configure_cpu_transcoder(new_crtc_state); - for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc, - intel_crtc_joined_pipe_mask(new_crtc_state)) { + for_each_intel_crtc_in_mask_priority(dev_priv, pipe_crtc, pipe, + intel_crtc_joined_pipe_mask(new_crtc_state), + intel_get_pipe_order_enable(new_crtc_state)) { const struct intel_crtc_state *pipe_crtc_state = intel_atomic_get_new_crtc_state(state, pipe_crtc); @@ -1780,8 +1818,9 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, intel_encoders_enable(state, crtc); - for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc, - intel_crtc_joined_pipe_mask(new_crtc_state)) { + for_each_intel_crtc_in_mask_priority(dev_priv, pipe_crtc, pipe, + intel_crtc_joined_pipe_mask(new_crtc_state), + intel_get_pipe_order_enable(new_crtc_state)) { const struct intel_crtc_state *pipe_crtc_state = intel_atomic_get_new_crtc_state(state, pipe_crtc); enum pipe hsw_workaround_pipe; @@ -1866,7 +1905,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state, const struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); struct drm_i915_private *i915 = to_i915(crtc->base.dev); - struct intel_crtc *pipe_crtc; + struct intel_crtc *pipe_crtc; enum pipe pipe; /* * FIXME collapse everything to one hook. @@ -1875,8 +1914,9 @@ static void hsw_crtc_disable(struct intel_atomic_state *state, intel_encoders_disable(state, crtc); intel_encoders_post_disable(state, crtc); - for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc, - intel_crtc_joined_pipe_mask(old_crtc_state)) { + for_each_intel_crtc_in_mask_priority(i915, pipe_crtc, pipe, + intel_crtc_joined_pipe_mask(old_crtc_state), + intel_get_pipe_order_disable(old_crtc_state)) { const struct intel_crtc_state *old_pipe_crtc_state = intel_atomic_get_old_crtc_state(state, pipe_crtc); @@ -1885,8 +1925,9 @@ static void hsw_crtc_disable(struct intel_atomic_state *state, intel_encoders_post_pll_disable(state, crtc); - for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc, - intel_crtc_joined_pipe_mask(old_crtc_state)) + for_each_intel_crtc_in_mask_priority(i915, pipe_crtc, pipe, + intel_crtc_joined_pipe_mask(old_crtc_state), + intel_get_pipe_order_disable(old_crtc_state)) intel_dmc_disable_pipe(i915, pipe_crtc->pipe); } diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index aafb2eac5e03..c44464ab3e1e 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -274,6 +274,11 @@ enum phy_fia { &(dev)->mode_config.crtc_list, \ base.head) +#define for_each_intel_crtc_in_mask_priority(__dev_priv, intel_crtc, __p, __mask, __priolist) \ + for_each_pipe(__dev_priv, __p) \ + for_each_if((__mask) & BIT(__priolist[__p])) \ + for_each_if(intel_crtc = intel_crtc_for_pipe(__dev_priv, __priolist[__p])) + #define for_each_intel_crtc_in_pipe_mask(dev, intel_crtc, pipe_mask) \ list_for_each_entry(intel_crtc, \ &(dev)->mode_config.crtc_list, \ @@ -424,6 +429,8 @@ enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port); bool is_trans_port_sync_mode(const struct intel_crtc_state *state); bool is_trans_port_sync_master(const struct intel_crtc_state *state); u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state); +const enum pipe *intel_get_pipe_order_enable(const struct intel_crtc_state *crtc_state); +const enum pipe *intel_get_pipe_order_disable(const struct intel_crtc_state *crtc_state); bool intel_crtc_is_joiner_slave(const struct intel_crtc_state *crtc_state); bool intel_crtc_is_joiner_master(const struct intel_crtc_state *crtc_state); u8 intel_crtc_joiner_slave_pipes(const struct intel_crtc_state *crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 2ac0835c1e8d..5a732b4bf19c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -990,7 +990,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, struct drm_dp_mst_atomic_payload *new_payload = drm_atomic_get_mst_payload_state(new_mst_state, connector->port); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); - struct intel_crtc *pipe_crtc; + struct intel_crtc *pipe_crtc; enum pipe pipe; bool last_mst_stream; intel_dp->active_mst_links--; @@ -999,8 +999,9 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, DISPLAY_VER(dev_priv) >= 12 && last_mst_stream && !intel_dp_mst_is_master_trans(old_crtc_state)); - for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc, - intel_crtc_joined_pipe_mask(old_crtc_state)) { + for_each_intel_crtc_in_mask_priority(dev_priv, pipe_crtc, pipe, + intel_crtc_joined_pipe_mask(old_crtc_state), + intel_get_pipe_order_disable(old_crtc_state)) { const struct intel_crtc_state *old_pipe_crtc_state = intel_atomic_get_old_crtc_state(state, pipe_crtc); @@ -1023,8 +1024,9 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, intel_ddi_disable_transcoder_func(old_crtc_state); - for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc, - intel_crtc_joined_pipe_mask(old_crtc_state)) { + for_each_intel_crtc_in_mask_priority(dev_priv, pipe_crtc, pipe, + intel_crtc_joined_pipe_mask(old_crtc_state), + intel_get_pipe_order_disable(old_crtc_state)) { const struct intel_crtc_state *old_pipe_crtc_state = intel_atomic_get_old_crtc_state(state, pipe_crtc); @@ -1213,7 +1215,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr); enum transcoder trans = pipe_config->cpu_transcoder; bool first_mst_stream = intel_dp->active_mst_links == 1; - struct intel_crtc *pipe_crtc; + struct intel_crtc *pipe_crtc; enum pipe pipe; drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder); @@ -1257,8 +1259,9 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, intel_enable_transcoder(pipe_config); - for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc, - intel_crtc_joined_pipe_mask(pipe_config)) { + for_each_intel_crtc_in_mask_priority(dev_priv, pipe_crtc, pipe, + intel_crtc_joined_pipe_mask(pipe_config), + intel_get_pipe_order_enable(pipe_config)) { const struct intel_crtc_state *pipe_crtc_state = intel_atomic_get_new_crtc_state(state, pipe_crtc);