From patchwork Mon May 20 18:58:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13668584 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 40670C25B77 for ; Mon, 20 May 2024 18:58:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 71FDC10E728; Mon, 20 May 2024 18:58:33 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="M93cye34"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5C20710E4F9 for ; Mon, 20 May 2024 18:58:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716231503; x=1747767503; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=YZJjWpCqTUGDViRlsS4VWpnvi6Dem1BKCMtkS1vxx/o=; b=M93cye34bCJXCXHTDIGuwRKKHawE9z7MBxNYawPRTHwKjr4BFSq4wKJ5 isDxuqejMVBA7nrnDX8Gwk+mECzW2mEICg3FZdMoFciAyDvmOZ6A4ahMi JplFyKfMORStzyR6nIsG2cvHw6wkRXHNkruFtopyHJRyKaLpNWyU+U8Dt S681xlaSLyL5jKEnBaYz8KjunZbgvI1Uz89dv32xFJR3dHMFgNqPLR4cG KN33GWy/d7OxiNRyHnfPaaPRGe0IHx7wJbX6OjqNcg01BYKk2GQkKRCph 0cA3wYtgMqXmgmWdwxGZa5Kp/43SbOEBr/lhibA8/d/wnlU72yAG/Y7Wh A==; X-CSE-ConnectionGUID: nvTIkrH5TnCB2v6kffbTow== X-CSE-MsgGUID: zC7VvyYbR5Kx8elCiS3oyA== X-IronPort-AV: E=McAfee;i="6600,9927,11078"; a="16218516" X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="16218516" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:23 -0700 X-CSE-ConnectionGUID: K+f7vb7HQn6EJuX23QePfA== X-CSE-MsgGUID: 4CqAbXXRS5+QgxSAiLs1lw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="37213843" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:22 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 04/21] drm/i915/dp: Sanitize intel_dp_get_link_train_fallback_values() Date: Mon, 20 May 2024 21:58:02 +0300 Message-ID: <20240520185822.3725844-5-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240520185822.3725844-1-imre.deak@intel.com> References: <20240520185822.3725844-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Reduce the indentation in intel_dp_get_link_train_fallback_values() by adding separate helpers to reduce the link rate and lane count. Also simplify things by passing crtc_state to the function. This also prepares for later patches in the patchset adding a limitation on how the link params are reduced. Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä --- .../drm/i915/display/intel_dp_link_training.c | 82 ++++++++++++------- 1 file changed, 51 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 4db293f256896..edc970036866a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1109,11 +1109,37 @@ static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp, return true; } +static int reduce_link_rate(struct intel_dp *intel_dp, int current_rate) +{ + int rate_index; + int new_rate; + + rate_index = intel_dp_rate_index(intel_dp->common_rates, + intel_dp->num_common_rates, + current_rate); + + if (rate_index <= 0) + return -1; + + new_rate = intel_dp_common_rate(intel_dp, rate_index - 1); + + return new_rate; +} + +static int reduce_lane_count(struct intel_dp *intel_dp, int current_lane_count) +{ + if (current_lane_count > 1) + return current_lane_count >> 1; + + return -1; +} + static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, - int link_rate, u8 lane_count) + const struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); - int index; + int new_link_rate; + int new_lane_count; /* * TODO: Enable fallback on MST links once MST link compute can handle @@ -1131,36 +1157,32 @@ static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, return 0; } - index = intel_dp_rate_index(intel_dp->common_rates, - intel_dp->num_common_rates, - link_rate); - if (index > 0) { - if (intel_dp_is_edp(intel_dp) && - !intel_dp_can_link_train_fallback_for_edp(intel_dp, - intel_dp_common_rate(intel_dp, index - 1), - lane_count)) { - drm_dbg_kms(&i915->drm, - "Retrying Link training for eDP with same parameters\n"); - return 0; - } - intel_dp->link.max_rate = intel_dp_common_rate(intel_dp, index - 1); - intel_dp->link.max_lane_count = lane_count; - } else if (lane_count > 1) { - if (intel_dp_is_edp(intel_dp) && - !intel_dp_can_link_train_fallback_for_edp(intel_dp, - intel_dp_max_common_rate(intel_dp), - lane_count >> 1)) { - drm_dbg_kms(&i915->drm, - "Retrying Link training for eDP with same parameters\n"); - return 0; - } - intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp); - intel_dp->link.max_lane_count = lane_count >> 1; - } else { + new_lane_count = crtc_state->lane_count; + new_link_rate = reduce_link_rate(intel_dp, crtc_state->port_clock); + if (new_link_rate < 0) { + new_lane_count = reduce_lane_count(intel_dp, crtc_state->lane_count); + new_link_rate = intel_dp_max_common_rate(intel_dp); + } + + if (new_lane_count < 0) { drm_err(&i915->drm, "Link Training Unsuccessful\n"); return -1; } + if (intel_dp_is_edp(intel_dp) && + !intel_dp_can_link_train_fallback_for_edp(intel_dp, new_link_rate, new_lane_count)) { + drm_dbg_kms(&i915->drm, + "Retrying Link training for eDP with same parameters\n"); + return 0; + } + + drm_dbg_kms(&i915->drm, "Reducing link parameters from %dx%d to %dx%d\n", + crtc_state->lane_count, crtc_state->port_clock, + new_lane_count, new_link_rate); + + intel_dp->link.max_rate = new_link_rate; + intel_dp->link.max_lane_count = new_lane_count; + return 0; } @@ -1178,9 +1200,7 @@ static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp, lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed with HOBL active, not enabling it from now on\n"); intel_dp->hobl_failed = true; - } else if (intel_dp_get_link_train_fallback_values(intel_dp, - crtc_state->port_clock, - crtc_state->lane_count)) { + } else if (intel_dp_get_link_train_fallback_values(intel_dp, crtc_state)) { return; }