From patchwork Mon May 20 18:58:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13668586 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 270A5C25B7A for ; Mon, 20 May 2024 18:58:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0A90210E751; Mon, 20 May 2024 18:58:34 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="OYdgqA+3"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3CE3610E572 for ; Mon, 20 May 2024 18:58:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716231505; x=1747767505; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=ocZts2b03pi+cwATm6taC9FipPB+Jt6NEu9Uisy9P5U=; b=OYdgqA+3Cqik2bux7/oKph+RFhnaAdVuGrhxMNwM90Bwuzrt94Z6Dqjt KdApwM0nIRL9unTxkOnhAsZ4rfXuQAQLsRe/tR/vfsKwZlCQZ4loQ0vwH nx031hVBB4wIeyqWzFoNM2BJkyudq6SGmy4Dk5HuOwvyEreYBqY7F+mvx DqI9MR379hoou1Me2dMkFNsQOeNBWAVzDOYmupBFHMJJcpP09suOfUl7f Ql+HGwJWmzRfk05hZw29u6tEWOk41cqGd1/brOFhOW+X2oqPfcKhLm+RF gIRRB5C5bb8+WLUkYdaQ7ROXB1bBHKyuTVWFLnhItIMHLMsOl6trgnYS0 w==; X-CSE-ConnectionGUID: +8aQiJxIQJ65VGtOUIodAg== X-CSE-MsgGUID: QkKkro5yRkqf7slz9KEjmw== X-IronPort-AV: E=McAfee;i="6600,9927,11078"; a="16218522" X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="16218522" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:25 -0700 X-CSE-ConnectionGUID: FvhOTswoQrSC7arRVIqj4g== X-CSE-MsgGUID: kEYykyRwR0e3bjLwqZBJng== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="37213847" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:24 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 06/21] drm/i915/dp: Use a commit modeset for link retraining MST links Date: Mon, 20 May 2024 21:58:04 +0300 Message-ID: <20240520185822.3725844-7-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240520185822.3725844-1-imre.deak@intel.com> References: <20240520185822.3725844-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Instead of direct calls to the link train functions, retrain the link via a commit modeset. The direct call means that the output port will be disabled/re-enabled while the rest of the pipeline (transcoder) is active, which doesn't seem to work on MST at least. It leads to underruns and black screen, presumedly because the transcoder is not disabled/re-enabled along the port. Leave switching to a commit modeset on SST for a later patchset, as that seems to work ok currently (though better to using a commit there too, due to the suppressed underruns). Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dp.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 81e620dd33bb7..120f7b420807b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5147,6 +5147,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct intel_crtc *crtc; u8 pipe_mask; + bool mst_output = false; int ret; if (!intel_dp_is_connected(intel_dp)) @@ -5177,6 +5178,11 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { + mst_output = true; + break; + } + /* Suppress underruns caused by re-training */ intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); if (crtc_state->has_pch_encoder) @@ -5184,16 +5190,23 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, intel_crtc_pch_transcoder(crtc), false); } + /* TODO: use a modeset for SST as well. */ + if (mst_output) { + ret = intel_modeset_commit_pipes(dev_priv, pipe_mask, ctx); + + if (ret && ret != -EDEADLK) + drm_dbg_kms(&dev_priv->drm, + "[ENCODER:%d:%s] link retraining failed: %pe\n", + encoder->base.base.id, encoder->base.name, + ERR_PTR(ret)); + + return ret; + } + for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { const struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); - /* retrain on the MST master transcoder */ - if (DISPLAY_VER(dev_priv) >= 12 && - intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) && - !intel_dp_mst_is_master_trans(crtc_state)) - continue; - intel_dp_check_frl_training(intel_dp); intel_dp_pcon_dsc_configure(intel_dp, crtc_state); intel_dp_start_link_train(intel_dp, crtc_state);