From patchwork Fri May 24 10:24:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 13673038 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 22A6AC25B74 for ; Fri, 24 May 2024 10:30:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C27BB10E8F2; Fri, 24 May 2024 10:30:32 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="kvF/5YSr"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id B817C10E8A0 for ; Fri, 24 May 2024 10:30:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716546619; x=1748082619; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HU+GwU9SNKG7kmk5sbJZ8cuoFJxLsOOf9kVlxsv5yc8=; b=kvF/5YSr+KWgt0OTSe+kyQRbLZjfmZ6jnZn8oIt3+MtyDHcarqSsWJDe duyTppVdnb7edFRPBj4GPUnpzX3epy99pFfUu5EUiwCvLuwHttWxk3z3t VJa4INg4p0YjSQWQi+bJh88VkFSWdWsbN0u2pUfW8ZT/YNacBnwh8L78K n5ngNSM3jjX5tvWRgn6NVpVOROb0B4KkSWF2Yyj2HN8C7BKel3H6KbK2i GcmGDuphTUxeCbWTAS/CDNtPfUKnMyUhab0NK+Tf1Upx4cccceFxhziIC z9c2dGTzIFiCsp5abePJiry3Y9FJ0v2iLx1f8L+uay4sFukI9tQsvL/QL g==; X-CSE-ConnectionGUID: mG1CQWtGQYyqUDcFRThexw== X-CSE-MsgGUID: vYrD4IoOQoKtYfFDr1ea7w== X-IronPort-AV: E=McAfee;i="6600,9927,11081"; a="15862710" X-IronPort-AV: E=Sophos;i="6.08,185,1712646000"; d="scan'208";a="15862710" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 May 2024 03:30:17 -0700 X-CSE-ConnectionGUID: 5DV0JTDNQwGrenFN+nNmpA== X-CSE-MsgGUID: SyPENktNQi2e8+9WGsb+8g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,185,1712646000"; d="scan'208";a="71385656" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa001.jf.intel.com with ESMTP; 24 May 2024 03:30:15 -0700 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com Subject: [PATCH v9 2/8] drm/i915: Update trans_vrr_ctl flag when cmrr is computed Date: Fri, 24 May 2024 15:54:26 +0530 Message-Id: <20240524102432.2499104-3-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240524102432.2499104-1-mitulkumar.ajitkumar.golani@intel.com> References: <20240524102432.2499104-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add/update trans_vrr_ctl flag when crtc_state->cmrr.enable is set, With this commit setting the stage for subsequent CMRR enablement. --v2: - Check pipe active state in cmrr enabling. [Jani] - Remove usage of bitwise OR on booleans. [Jani] - Revert unrelated changes. [Jani] - Update intel_vrr_enable, vrr and cmrr enable conditions. [Jani] - Simplify whole if-ladder in intel_vrr_enable. [Jani] - Revert patch restructuring mistakes in intel_vrr_get_config. [Jani] --v3: - Check pipe active state in cmrr disabling.[Jani] - Correct messed up condition in intel_vrr_enable. [Jani] --v4: - Removing RFC tag. --v5: - CMRR handling in co-existatnce of LRR and DRRS. --v7: - Rebase on top of AS SDP merge. --v8: - Remove cmrr_enabling/disabling and update commit message. (Ankit) Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/intel_vrr.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index b96a8b2e7083..3b250e92af98 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -277,15 +277,20 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) intel_de_write(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder), TRANS_PUSH_EN); - if (HAS_AS_SDP(dev_priv)) intel_de_write(dev_priv, TRANS_VRR_VSYNC(dev_priv, cpu_transcoder), VRR_VSYNC_END(crtc_state->vrr.vsync_end) | VRR_VSYNC_START(crtc_state->vrr.vsync_start)); - intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder), - VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); + if (crtc_state->cmrr.enable) { + intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder), + VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE | + trans_vrr_ctl(crtc_state)); + } else { + intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder), + VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); + } } void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)