From patchwork Fri May 24 10:24:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 13673040 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6EE1BC25B74 for ; Fri, 24 May 2024 10:30:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C818D10E906; Fri, 24 May 2024 10:30:33 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="OBTM7jAV"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7572F10E906 for ; Fri, 24 May 2024 10:30:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716546626; x=1748082626; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sUo1sxcg0LXJNmYXKF4IJJSqO9DNrhg6ikktmWnYeqw=; b=OBTM7jAVs3eYG7AF1bAddqoOwZxtCss0V1/CQfsvxQJVvbq1C0DOX0SW ZQpiVKsVbO8w/tBHk6nU+fKf6qwtWaDxhXjZaK3619m6mPgGqZqV6sJCO WjCZQ17zaY95Ue9TV1ynfcBZsiqPAzYgLYu+EgvtSFDcQ+/A7z3yWwKlg +J2HVkkgX0+y8pHomUhD2c5u+fukrAjoB0s5JCMD/dl4tmQ+Oex1HDg/J 4u3EdEbDm//ydTV5rXo/jLuIm8kJEiPMw4YaN9GaQObHsa6HhfmV5mblb NjqdiM3eE+4XNb4EPksqO4g4WXcCpPJ//V8/H+ijxCQj68rdxLA6ktVnL A==; X-CSE-ConnectionGUID: DQsNs5HCQzCQQvcnUzGilQ== X-CSE-MsgGUID: Z7cKmK0lRQKCssFslh0Ztw== X-IronPort-AV: E=McAfee;i="6600,9927,11081"; a="15862731" X-IronPort-AV: E=Sophos;i="6.08,185,1712646000"; d="scan'208";a="15862731" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 May 2024 03:30:20 -0700 X-CSE-ConnectionGUID: CSEK5kZ3SHOeGN51E3H6Yw== X-CSE-MsgGUID: C4NpnR2sS5q2pUpWV2I/HA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,185,1712646000"; d="scan'208";a="71385688" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa001.jf.intel.com with ESMTP; 24 May 2024 03:30:19 -0700 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com Subject: [PATCH v9 5/8] drm/i915/display: Add support for pack and unpack Date: Fri, 24 May 2024 15:54:29 +0530 Message-Id: <20240524102432.2499104-6-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240524102432.2499104-1-mitulkumar.ajitkumar.golani@intel.com> References: <20240524102432.2499104-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add support of pack and unpack for target_rr_divider. --v2: - Set Target Refresh Rate Divider bit when related AS SDP bit is set (Ankit). Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/intel_dp.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index c0a3b6d50681..15aab14c4206 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4230,6 +4230,9 @@ static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp, sdp->db[3] = as_sdp->target_rr & 0xFF; sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3; + if (as_sdp->target_rr_divider) + sdp->db[4] |= 0x20; + return length; } @@ -4410,6 +4413,7 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp, as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE; as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1]; as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3); + as_sdp->target_rr_divider = sdp->db[4] & 0x20; return 0; }