diff mbox series

[v3,06/20] drm/i915/psr: Add Panel Replay support to intel_psr2_config_et_valid

Message ID 20240527072220.3294769-7-jouni.hogander@intel.com (mailing list archive)
State New, archived
Headers show
Series Panel Replay eDP support | expand

Commit Message

Hogander, Jouni May 27, 2024, 7:22 a.m. UTC 
Early Transport is possible and in our HW mandatory on eDP Panel
Replay. Add parameter to intel_psr2_config_et_valid to differentiate
validity check for Panel Replay.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 21 ++++++++++++---------
 1 file changed, 12 insertions(+), 9 deletions(-)

Comments

Manna, Animesh May 29, 2024, 7:20 a.m. UTC | #1 
> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Monday, May 27, 2024 12:52 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Kahola, Mika
> <mika.kahola@intel.com>; Hogander, Jouni <jouni.hogander@intel.com>
> Subject: [PATCH v3 06/20] drm/i915/psr: Add Panel Replay support to
> intel_psr2_config_et_valid
> 
> Early Transport is possible and in our HW mandatory on eDP Panel
> Replay. Add parameter to intel_psr2_config_et_valid to differentiate
> validity check for Panel Replay.
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>

LGTM.
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
 
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 21 ++++++++++++---------
>  1 file changed, 12 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 19f8ac12f995..a01c2173a2e5 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -673,16 +673,17 @@ static void hsw_psr_setup_aux(struct intel_dp
> *intel_dp)
>  		       aux_ctl);
>  }
> 
> -static bool psr2_su_region_et_valid(struct intel_dp *intel_dp)
> +static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, bool
> panel_replay)
>  {
>  	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> 
> -	if (DISPLAY_VER(i915) >= 20 &&
> -	    intel_dp->psr_dpcd[0] ==
> DP_PSR2_WITH_Y_COORD_ET_SUPPORTED &&
> -	    !(intel_dp->psr.debug &
> I915_PSR_DEBUG_SU_REGION_ET_DISABLE))
> -		return true;
> +	if (DISPLAY_VER(i915) < 20 || !intel_dp_is_edp(intel_dp) ||
> +	    intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE)
> +		return false;
> 
> -	return false;
> +	return panel_replay ?
> +		intel_dp->pr_dpcd &
> DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT :
> +		intel_dp->psr_dpcd[0] !=
> DP_PSR2_WITH_Y_COORD_ET_SUPPORTED;
>  }
> 
>  static unsigned int intel_psr_get_enable_sink_offset(struct intel_dp
> *intel_dp)
> @@ -709,7 +710,8 @@ void intel_psr_enable_sink(struct intel_dp *intel_dp,
>  					   DP_ALPM_ENABLE |
> 
> DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
> 
> -			if (psr2_su_region_et_valid(intel_dp))
> +			if (psr2_su_region_et_valid(intel_dp,
> +						    intel_dp-
> >psr.panel_replay_enabled))
>  				dpcd_val |=
> DP_PSR_ENABLE_SU_REGION_ET;
>  		}
> 
> @@ -978,7 +980,8 @@ static void hsw_activate_psr2(struct intel_dp
> *intel_dp)
>  			       PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder),
> 0);
>  	}
> 
> -	if (psr2_su_region_et_valid(intel_dp))
> +	if (psr2_su_region_et_valid(intel_dp,
> +				    intel_dp->psr.panel_replay_enabled))
>  		val |= LNL_EDP_PSR2_SU_REGION_ET_ENABLE;
> 
>  	/*
> @@ -1587,7 +1590,7 @@ static bool intel_psr2_config_valid(struct intel_dp
> *intel_dp,
> 
>  	tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
> 
> -	if (psr2_su_region_et_valid(intel_dp))
> +	if (psr2_su_region_et_valid(intel_dp, false))
>  		crtc_state->enable_psr2_su_region_et = true;
> 
>  	return true;
> --
> 2.34.1
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 19f8ac12f995..a01c2173a2e5 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -673,16 +673,17 @@  static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
 		       aux_ctl);
 }
 
-static bool psr2_su_region_et_valid(struct intel_dp *intel_dp)
+static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, bool panel_replay)
 {
 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 
-	if (DISPLAY_VER(i915) >= 20 &&
-	    intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED &&
-	    !(intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE))
-		return true;
+	if (DISPLAY_VER(i915) < 20 || !intel_dp_is_edp(intel_dp) ||
+	    intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE)
+		return false;
 
-	return false;
+	return panel_replay ?
+		intel_dp->pr_dpcd & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT :
+		intel_dp->psr_dpcd[0] != DP_PSR2_WITH_Y_COORD_ET_SUPPORTED;
 }
 
 static unsigned int intel_psr_get_enable_sink_offset(struct intel_dp *intel_dp)
@@ -709,7 +710,8 @@  void intel_psr_enable_sink(struct intel_dp *intel_dp,
 					   DP_ALPM_ENABLE |
 					   DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
 
-			if (psr2_su_region_et_valid(intel_dp))
+			if (psr2_su_region_et_valid(intel_dp,
+						    intel_dp->psr.panel_replay_enabled))
 				dpcd_val |= DP_PSR_ENABLE_SU_REGION_ET;
 		}
 
@@ -978,7 +980,8 @@  static void hsw_activate_psr2(struct intel_dp *intel_dp)
 			       PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder), 0);
 	}
 
-	if (psr2_su_region_et_valid(intel_dp))
+	if (psr2_su_region_et_valid(intel_dp,
+				    intel_dp->psr.panel_replay_enabled))
 		val |= LNL_EDP_PSR2_SU_REGION_ET_ENABLE;
 
 	/*
@@ -1587,7 +1590,7 @@  static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 
 	tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
 
-	if (psr2_su_region_et_valid(intel_dp))
+	if (psr2_su_region_et_valid(intel_dp, false))
 		crtc_state->enable_psr2_su_region_et = true;
 
 	return true;