diff mbox series

[4/7] drm/i915: Add a separate defintiion for PIPE_CRC_RES_HSW

Message ID 20240531115342.2763-5-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: Clean up the CRC registers | expand

Commit Message

Ville Syrjala May 31, 2024, 11:53 a.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On hsw+ we only have one CRC result registers, instead of the
five we have on ivb, and some of the others have been repurposed
to serve other CRC related purposed.

Since the hsw+ vs. pre-hsw register operate quite diffently
let's add a separate definition for the hsw+ variant to make the
situation a bit more clear. Also since we only use this from a
hsw+ codepath there is no real benefit to be had with reusing
the ivb register definition.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_irq.c   | 2 +-
 drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h | 5 +++++
 2 files changed, 6 insertions(+), 1 deletion(-)

Comments

Jani Nikula May 31, 2024, 1:06 p.m. UTC | #1 
Subject: *definition

On Fri, 31 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> On hsw+ we only have one CRC result registers, instead of the

*register

> five we have on ivb, and some of the others have been repurposed
> to serve other CRC related purposed.

*purposes

>
> Since the hsw+ vs. pre-hsw register operate quite diffently

*differently

> let's add a separate definition for the hsw+ variant to make the
> situation a bit more clear. Also since we only use this from a
> hsw+ codepath there is no real benefit to be had with reusing
> the ivb register definition.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 7db87dfcb12a..d2d70b81aef9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -357,7 +357,7 @@  static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
 				     enum pipe pipe)
 {
 	display_pipe_crc_irq_handler(dev_priv, pipe,
-				     intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)),
+				     intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_HSW(pipe)),
 				     0, 0, 0, 0);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h
index a1217a4d6f2e..d06ff3516dbc 100644
--- a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h
@@ -92,4 +92,9 @@ 
 #define _PIPE_CRC_RES_5_B_IVB		0x61074
 #define PIPE_CRC_RES_5_IVB(pipe)		_MMIO_PIPE(pipe, _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB)
 
+/* hsw+ */
+#define _PIPE_CRC_RES_A_HSW		0x60064
+#define _PIPE_CRC_RES_B_HSW		0x61064
+#define PIPE_CRC_RES_HSW(pipe)			_MMIO_PIPE(pipe, _PIPE_CRC_RES_A_HSW, _PIPE_CRC_RES_B_HSW)
+
 #endif /* __INTEL_PIPE_CRC_REGS_H__ */