diff mbox series

drm/i915: Support RGB16161616_64B compressed formats

Message ID 20240603084745.1881-1-melanie.lobo@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: Support RGB16161616_64B compressed formats | expand

Commit Message

Melanie Lobo June 3, 2024, 8:47 a.m. UTC 
Add support for a RGB64(FP16) format where each color component is a
16-bit floating point value. FP16 format which is a binary
floating-point computer number format that occupies 16 bits in computer
memory. Platform shall render compression in display engine to receive
FP16 compressed formats.

This kernel change was tested with IGT patch,
https://patchwork.freedesktop.org/series/134353/
https://lore.kernel.org/all/20240603081607.30930-1-melanie.lobo@intel.com/

Test-with: 20240603081607.30930-1-melanie.lobo@intel.com

Credits: Juha-Pekka <juha-pekka.heikkila@intel.com>
Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Cc: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Cc: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Melanie Lobo <melanie.lobo@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fb.c        | 18 ++++++++++++++++++
 .../gpu/drm/i915/display/skl_universal_plane.c |  4 ++--
 2 files changed, 20 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index b6638726949d..88b8489f4ed2 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -91,6 +91,11 @@  static const struct drm_format_info gen12_ccs_formats[] = {
 	{ .format = DRM_FORMAT_P016, .num_planes = 4,
 	  .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
 	  .hsub = 2, .vsub = 2, .is_yuv = true },
+	{ .format = DRM_FORMAT_XRGB16161616F, .depth = 64, .num_planes = 2,
+	  .char_per_block = { 8, 1}, .block_w = { 1, 4}, .block_h = { 1, 2}, .hsub = 1, .vsub = 1},
+	{ .format = DRM_FORMAT_ARGB16161616F, .depth = 64, .num_planes = 2,
+	  .char_per_block = { 8, 1}, .block_w = { 1, 4}, .block_h = { 1, 2},
+	  .hsub = 1, .vsub = 1, .has_alpha = true},
 };
 
 /*
@@ -421,6 +426,8 @@  static bool plane_has_modifier(struct drm_i915_private *i915,
 			       u8 plane_caps,
 			       const struct intel_modifier_desc *md)
 {
+	const struct drm_format_info *info;
+
 	if (!IS_DISPLAY_VER(i915, md->display_ver.from, md->display_ver.until))
 		return false;
 
@@ -435,6 +442,17 @@  static bool plane_has_modifier(struct drm_i915_private *i915,
 	    HAS_FLAT_CCS(i915) != !md->ccs.packed_aux_planes)
 		return false;
 
+	/* Check if CSS modifier and FP16 format is supported on different platforms */
+	info = lookup_format_info(md->formats, md->format_count, DRM_FORMAT_XRGB16161616F);
+	if (intel_fb_is_ccs_modifier(md->modifier) && info &&
+	    info->format == DRM_FORMAT_XRGB16161616F && DISPLAY_VER(i915) < 12)
+	       return false;
+
+	info = lookup_format_info(md->formats, md->format_count, DRM_FORMAT_ARGB16161616F);
+	if (intel_fb_is_ccs_modifier(md->modifier) && info &&
+	    info->format == DRM_FORMAT_ARGB16161616F && DISPLAY_VER(i915) < 12)
+		return false;
+
 	return true;
 }
 
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index b7678b8a7f3d..9255affed543 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2184,6 +2184,8 @@  static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
 	case DRM_FORMAT_XBGR8888:
 	case DRM_FORMAT_ARGB8888:
 	case DRM_FORMAT_ABGR8888:
+	case DRM_FORMAT_XRGB16161616F:
+	case DRM_FORMAT_ARGB16161616F:
 		if (intel_fb_is_ccs_modifier(modifier))
 			return true;
 		fallthrough;
@@ -2208,8 +2210,6 @@  static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
 	case DRM_FORMAT_C8:
 	case DRM_FORMAT_XBGR16161616F:
 	case DRM_FORMAT_ABGR16161616F:
-	case DRM_FORMAT_XRGB16161616F:
-	case DRM_FORMAT_ARGB16161616F:
 	case DRM_FORMAT_Y210:
 	case DRM_FORMAT_Y212:
 	case DRM_FORMAT_Y216: