From patchwork Mon Jun 3 13:00:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 13683805 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0E6E1C27C53 for ; Mon, 3 Jun 2024 13:01:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3344B10E0F4; Mon, 3 Jun 2024 13:01:17 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="JIa6sR5D"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7ACD110E341 for ; Mon, 3 Jun 2024 13:01:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1717419672; x=1748955672; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nhUcigmo3lDr1aXgVCGSCQ7jpMQIvzB680lGsPovl34=; b=JIa6sR5DyNz5wCMZ7pD7W4KY0a+epFvNx+9lnQKMmfPCA3sfsG0FmvzQ 0n6RklfrFzv3g28hfPCfDqeRXTQkwIA5+aiMCjtp2o95l/3O6nAWu6+sQ s3NVsiWngacgvPtKB2P6gLQEK1lc4LU5YzdVlksYAoPoGwX9jhJKUnvLm GnOuBqkBee1GA181zlJLZ9mPu/6A99sFpwivtUiP4TzDN8J2gyuiN0vp3 SK37FMKsQGdc1YmaYNB8l9sbFZk3KNj6IB2f9tw+XcXxjPC1g6kxfYqP6 /1rkJzSpwaQybin9H2bNOC9of5fVJQRvOF61jD4xt4rJjKnVMs7/rQfbk g==; X-CSE-ConnectionGUID: lkAjDaQBRjKIpiV6CEzbYA== X-CSE-MsgGUID: CG9WTUMcQHqemuzHJ/UE6w== X-IronPort-AV: E=McAfee;i="6600,9927,11092"; a="13774468" X-IronPort-AV: E=Sophos;i="6.08,211,1712646000"; d="scan'208";a="13774468" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2024 06:01:06 -0700 X-CSE-ConnectionGUID: bskNOQp2T2W4IPQhWbFVxA== X-CSE-MsgGUID: GJ//46ctSaugMOVfUAphZA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,211,1712646000"; d="scan'208";a="41291752" Received: from jgulati-mobl.ger.corp.intel.com (HELO jhogande-mobl1.intel.com) ([10.251.212.183]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jun 2024 06:01:04 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Cc: animesh.manna@intel.com, mika.kahola@intel.com, =?utf-8?q?Jouni_H=C3=B6g?= =?utf-8?q?ander?= Subject: [PATCH v5 05/19] drm/i915/psr: Add Panel Replay support to intel_psr2_config_et_valid Date: Mon, 3 Jun 2024 16:00:29 +0300 Message-Id: <20240603130043.2615716-6-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240603130043.2615716-1-jouni.hogander@intel.com> References: <20240603130043.2615716-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Early Transport is possible and in our HW mandatory on eDP Panel Replay. Add parameter to intel_psr2_config_et_valid to differentiate validity check for Panel Replay. Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 4a4124a92a0d..fd861db96db8 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -674,16 +674,17 @@ static void hsw_psr_setup_aux(struct intel_dp *intel_dp) aux_ctl); } -static bool psr2_su_region_et_valid(struct intel_dp *intel_dp) +static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, bool panel_replay) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); - if (DISPLAY_VER(i915) >= 20 && - intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED && - !(intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE)) - return true; + if (DISPLAY_VER(i915) < 20 || !intel_dp_is_edp(intel_dp) || + intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE) + return false; - return false; + return panel_replay ? + intel_dp->pr_dpcd & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT : + intel_dp->psr_dpcd[0] != DP_PSR2_WITH_Y_COORD_ET_SUPPORTED; } static unsigned int intel_psr_get_enable_sink_offset(struct intel_dp *intel_dp) @@ -1355,7 +1356,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); - if (psr2_su_region_et_valid(intel_dp)) + if (psr2_su_region_et_valid(intel_dp, crtc_state->has_panel_replay)) crtc_state->enable_psr2_su_region_et = true; return true;