| Message ID | 20240605111832.21373-5-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: bdw+ pipe interrupt stuff | expand |
On Wed, 05 Jun 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > GEN9_PIPE_PLANE_FLIP_DONE() only works for planes 1-4. Extend > it handle planes 5-7 as well. Somewhat annoyingly the bits are > spread around into two distinct clumps. > > Currently this doesn't achieve anything, but if we ever extend > async flip support to more than just the first plane then we'll > need this. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 8e1053c60284..4d5438ce73a2 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -2631,6 +2631,9 @@ > #define GEN11_PIPE_PLANE6_FAULT REG_BIT(21) /* icl/tgl */ > #define GEN11_PIPE_PLANE5_FAULT REG_BIT(20) /* icl+ */ > #define GEN12_PIPE_VBLANK_UNMOD REG_BIT(19) /* tgl+ */ > +#define GEN11_PIPE_PLANE7_FLIP_DONE REG_BIT(18) /* icl/tgl */ > +#define GEN11_PIPE_PLANE6_FLIP_DONE REG_BIT(17) /* icl/tgl */ Need to be careful with these, as they're pipe DMC error and plane ATS fault on mtl+. Reviewed-by: Jani Nikula <jani.nikula@intel.com> > +#define GEN11_PIPE_PLANE5_FLIP_DONE REG_BIT(16) /* icl+ */ > #define GEN9_PIPE_CURSOR_FAULT REG_BIT(11) /* skl+ */ > #define GEN9_PIPE_PLANE4_FAULT REG_BIT(10) /* skl+ */ > #define GEN8_PIPE_CURSOR_FAULT REG_BIT(10) /* bdw */ > @@ -2645,7 +2648,8 @@ > #define GEN9_PIPE_PLANE2_FLIP_DONE REG_BIT(4) /* skl+ */ > #define GEN8_PIPE_PRIMARY_FLIP_DONE REG_BIT(4) /* bdw */ > #define GEN9_PIPE_PLANE1_FLIP_DONE REG_BIT(3) /* skl+ */ > -#define GEN9_PIPE_PLANE_FLIP_DONE(p) REG_BIT(3 + (p)) /* skl+ */ > +#define GEN9_PIPE_PLANE_FLIP_DONE(plane_id) \ > + REG_BIT(((plane_id) >= PLANE_5 ? 16 - PLANE_5 : 3 - PLANE_1) + (plane_id)) /* skl+ */ > #define GEN8_PIPE_SCAN_LINE_EVENT REG_BIT(2) > #define GEN8_PIPE_VSYNC REG_BIT(1) > #define GEN8_PIPE_VBLANK REG_BIT(0)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8e1053c60284..4d5438ce73a2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2631,6 +2631,9 @@ #define GEN11_PIPE_PLANE6_FAULT REG_BIT(21) /* icl/tgl */ #define GEN11_PIPE_PLANE5_FAULT REG_BIT(20) /* icl+ */ #define GEN12_PIPE_VBLANK_UNMOD REG_BIT(19) /* tgl+ */ +#define GEN11_PIPE_PLANE7_FLIP_DONE REG_BIT(18) /* icl/tgl */ +#define GEN11_PIPE_PLANE6_FLIP_DONE REG_BIT(17) /* icl/tgl */ +#define GEN11_PIPE_PLANE5_FLIP_DONE REG_BIT(16) /* icl+ */ #define GEN9_PIPE_CURSOR_FAULT REG_BIT(11) /* skl+ */ #define GEN9_PIPE_PLANE4_FAULT REG_BIT(10) /* skl+ */ #define GEN8_PIPE_CURSOR_FAULT REG_BIT(10) /* bdw */ @@ -2645,7 +2648,8 @@ #define GEN9_PIPE_PLANE2_FLIP_DONE REG_BIT(4) /* skl+ */ #define GEN8_PIPE_PRIMARY_FLIP_DONE REG_BIT(4) /* bdw */ #define GEN9_PIPE_PLANE1_FLIP_DONE REG_BIT(3) /* skl+ */ -#define GEN9_PIPE_PLANE_FLIP_DONE(p) REG_BIT(3 + (p)) /* skl+ */ +#define GEN9_PIPE_PLANE_FLIP_DONE(plane_id) \ + REG_BIT(((plane_id) >= PLANE_5 ? 16 - PLANE_5 : 3 - PLANE_1) + (plane_id)) /* skl+ */ #define GEN8_PIPE_SCAN_LINE_EVENT REG_BIT(2) #define GEN8_PIPE_VSYNC REG_BIT(1) #define GEN8_PIPE_VBLANK REG_BIT(0)