diff mbox series

[v7,01/18] drm/i915/psr: Set SU area width as pipe src width

Message ID 20240611121243.3366990-2-jouni.hogander@intel.com (mailing list archive)
State New, archived
Headers show
Series Panel Replay eDP support | expand

Commit Message

Hogander, Jouni June 11, 2024, 12:12 p.m. UTC 
Currently SU area width is set as MAX_INT. This is causing
problems. Instead set it as pipe src width.

Fixes: 86b26b6aeac7 ("drm/i915/psr: Carry su area in crtc_state")

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 1cce9713a960..66ab8abd0a04 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2316,7 +2316,7 @@  int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 
 	crtc_state->psr2_su_area.x1 = 0;
 	crtc_state->psr2_su_area.y1 = -1;
-	crtc_state->psr2_su_area.x2 = INT_MAX;
+	crtc_state->psr2_su_area.x2 = drm_rect_width(&crtc_state->pipe_src);
 	crtc_state->psr2_su_area.y2 = -1;
 
 	/*