| Message ID | 20240618053026.3268759-6-jouni.hogander@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Panel Replay eDP more prepare patches | expand |
> -----Original Message----- > From: Hogander, Jouni <jouni.hogander@intel.com> > Sent: Tuesday, June 18, 2024 11:00 AM > To: intel-gfx@lists.freedesktop.org > Cc: Manna, Animesh <animesh.manna@intel.com>; Kahola, Mika > <mika.kahola@intel.com>; Hogander, Jouni <jouni.hogander@intel.com> > Subject: [PATCH 5/9] drm/i915/psr: Disable PSR2 SU Region ET if enable_psr > module parameter is set > > Currently PSR2 SU Region Early Transport is enabled by default on Lunarlake > if panel supports it despite enable_psr module parameter value. This patch > makes it possible for user to limit used PSR mode and prevent SU Region > Early Transport by setting enable_psr as 2. With default (-1) PSR2 SU Region > Early Transport is allowed. > > v2: fix/improve commit desciption > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 13 ++++++++++++- > 1 file changed, 12 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index cfce0fe05d92..800cfeabc139 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -235,6 +235,16 @@ static bool psr2_global_enabled(struct intel_dp > *intel_dp) > } > } > > +static bool psr2_su_region_et_global_enabled(struct intel_dp *intel_dp) > +{ > + struct drm_i915_private *i915 = dp_to_i915(intel_dp); > + > + if (i915->display.params.enable_psr != -1) > + return false; > + > + return true; > +} > + > static bool panel_replay_global_enabled(struct intel_dp *intel_dp) { > struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -683,7 > +693,8 @@ static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, > bool panel_replay > > return panel_replay ? > intel_dp->pr_dpcd & > DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT : > - intel_dp->psr_dpcd[0] == > DP_PSR2_WITH_Y_COORD_ET_SUPPORTED; > + intel_dp->psr_dpcd[0] == > DP_PSR2_WITH_Y_COORD_ET_SUPPORTED && > + psr2_su_region_et_global_enabled(intel_dp); > } > > static void _panel_replay_enable_sink(struct intel_dp *intel_dp, > -- > 2.34.1
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index cfce0fe05d92..800cfeabc139 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -235,6 +235,16 @@ static bool psr2_global_enabled(struct intel_dp *intel_dp) } } +static bool psr2_su_region_et_global_enabled(struct intel_dp *intel_dp) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + + if (i915->display.params.enable_psr != -1) + return false; + + return true; +} + static bool panel_replay_global_enabled(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -683,7 +693,8 @@ static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, bool panel_replay return panel_replay ? intel_dp->pr_dpcd & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT : - intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED; + intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED && + psr2_su_region_et_global_enabled(intel_dp); } static void _panel_replay_enable_sink(struct intel_dp *intel_dp,
Currently PSR2 SU Region Early Transport is enabled by default on Lunarlake if panel supports it despite enable_psr module parameter value. This patch makes it possible for user to limit used PSR mode and prevent SU Region Early Transport by setting enable_psr as 2. With default (-1) PSR2 SU Region Early Transport is allowed. v2: fix/improve commit desciption Signed-off-by: Jouni Högander <jouni.hogander@intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-)