diff mbox series

[1/2] drm/i915/psr: Add return bool value for hsw_activate_psr1

Message ID 20240619043756.2068376-2-suraj.kandpal@intel.com (mailing list archive)
State New, archived
Headers show
Series Implement WA to fix increased power usage | expand

Commit Message

Kandpal, Suraj June 19, 2024, 4:37 a.m. UTC
Convert hsw_activate_psr1 from void to bool as going forward
there is a chance psr1 is not enabled.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

Comments

Shankar, Uma Aug. 22, 2024, 5:09 a.m. UTC | #1
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Suraj
> Kandpal
> Sent: Wednesday, June 19, 2024 10:08 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Murthy, Arun R
> <arun.r.murthy@intel.com>; Hogander, Jouni <jouni.hogander@intel.com>;
> jani.nikula@linux.intel.com; Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: [PATCH 1/2] drm/i915/psr: Add return bool value for hsw_activate_psr1
> 
> Convert hsw_activate_psr1 from void to bool as going forward there is a chance
> psr1 is not enabled.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 920186c2264d..080bf5e51148 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -808,7 +808,7 @@ static u8 psr_compute_idle_frames(struct intel_dp
> *intel_dp)
>  	return idle_frames;
>  }
> 
> -static void hsw_activate_psr1(struct intel_dp *intel_dp)
> +static bool hsw_activate_psr1(struct intel_dp *intel_dp)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	enum transcoder cpu_transcoder = intel_dp->psr.transcoder; @@ -836,6
> +836,8 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
> 
>  	intel_de_rmw(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder),
>  		     ~EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK, val);
> +
> +	return true;
>  }
> 
>  static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp) @@ -1560,6
> +1562,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp)  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
> +	bool ret = true;
> 
>  	drm_WARN_ON(&dev_priv->drm,
>  		    transcoder_has_psr2(dev_priv, cpu_transcoder) && @@ -
> 1578,9 +1581,9 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
>  	else if (intel_dp->psr.sel_update_enabled)
>  		hsw_activate_psr2(intel_dp);
>  	else
> -		hsw_activate_psr1(intel_dp);
> +		ret = hsw_activate_psr1(intel_dp);
> 
> -	intel_dp->psr.active = true;
> +	intel_dp->psr.active = ret;
>  }
> 
>  static u32 wa_16013835468_bit_get(struct intel_dp *intel_dp)
> --
> 2.43.2
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 920186c2264d..080bf5e51148 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -808,7 +808,7 @@  static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
 	return idle_frames;
 }
 
-static void hsw_activate_psr1(struct intel_dp *intel_dp)
+static bool hsw_activate_psr1(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
@@ -836,6 +836,8 @@  static void hsw_activate_psr1(struct intel_dp *intel_dp)
 
 	intel_de_rmw(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder),
 		     ~EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK, val);
+
+	return true;
 }
 
 static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
@@ -1560,6 +1562,7 @@  static void intel_psr_activate(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
+	bool ret = true;
 
 	drm_WARN_ON(&dev_priv->drm,
 		    transcoder_has_psr2(dev_priv, cpu_transcoder) &&
@@ -1578,9 +1581,9 @@  static void intel_psr_activate(struct intel_dp *intel_dp)
 	else if (intel_dp->psr.sel_update_enabled)
 		hsw_activate_psr2(intel_dp);
 	else
-		hsw_activate_psr1(intel_dp);
+		ret = hsw_activate_psr1(intel_dp);
 
-	intel_dp->psr.active = true;
+	intel_dp->psr.active = ret;
 }
 
 static u32 wa_16013835468_bit_get(struct intel_dp *intel_dp)