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[v2,1/1] drm/i915/display: WA for Re-initialize dispcnlunitt1 xosc clock

Message ID 20240619101711.860988-2-mitulkumar.ajitkumar.golani@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/display: WA for Re-initialize dispcnlunitt1 xosc clock | expand

Commit Message

Golani, Mitulkumar Ajitkumar June 19, 2024, 10:17 a.m. UTC 
The dispcnlunit1_cp_xosc_clk should be de-asserted in display off
and only asserted in display on. But during observation it found
clk remains active in display OFF. As workaround, Display driver
shall execute set-reset sequence at the end of the Initialize
Sequence.

Wa_14020225554

--v2:
- Update workaround number in commit message.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 8 ++++++++
 1 file changed, 8 insertions(+)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index e288a1b21d7e..0d8875fa5ef2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1704,6 +1704,14 @@  static void icl_display_core_init(struct drm_i915_private *dev_priv,
 	/* Wa_14011503030:xelpd */
 	if (DISPLAY_VER(dev_priv) == 13)
 		intel_de_write(dev_priv, XELPD_DISPLAY_ERR_FATAL_MASK, ~0);
+
+	/* Wa_14020225554 */
+	if (DISPLAY_VER(dev_priv) == 20) {
+		intel_de_write(dev_priv, SOUTH_DSPCLK_GATE_D,
+			       PCH_GMBUSUNIT_CLOCK_GATE_DISABLE);
+		intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D,
+			     PCH_GMBUSUNIT_CLOCK_GATE_DISABLE, 0);
+	}
 }
 
 static void icl_display_core_uninit(struct drm_i915_private *dev_priv)