diff mbox series

[5/5] drm/i915: Allow async flips with CCS on ICL

Message ID 20240624150538.24102-6-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: Enable CCS+10bpc and CCS+async flips | expand

Commit Message

Ville Syrjälä June 24, 2024, 3:05 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Apparently ICL can do async flips with CCS. In fact it already
seems to work on GLK, but apparently can lead to underruns there
so we'll only enable it for ICL.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 21 +++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0b0c5ef1d48e..eeba224b9f25 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6243,7 +6243,26 @@  static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct in
 				return -EINVAL;
 			}
 			break;
-
+		case I915_FORMAT_MOD_Y_TILED_CCS:
+		case I915_FORMAT_MOD_Yf_TILED_CCS:
+			/*
+			 * Display WA #0731: skl
+			 * WaDisableRCWithAsyncFlip: skl
+			 * "When render decompression is enabled, hardware
+			 *  internally converts the Async flips to Sync flips."
+			 *
+			 * Display WA #1159: glk
+			 * "Async flip with render compression may result in
+			 *  intermittent underrun corruption."
+			 */
+			if (DISPLAY_VER(i915) < 11) {
+				drm_dbg_kms(&i915->drm,
+					    "[PLANE:%d:%s] Modifier 0x%llx does not support async flip on display ver %d\n",
+					    plane->base.base.id, plane->base.name,
+					    new_plane_state->hw.fb->modifier, DISPLAY_VER(i915));
+				return -EINVAL;
+			}
+			break;
 		case I915_FORMAT_MOD_X_TILED:
 		case I915_FORMAT_MOD_Y_TILED:
 		case I915_FORMAT_MOD_Yf_TILED: