diff mbox series

i915/perf: Remove code to update PWR_CLK_STATE for gen12

Message ID 20240629005643.3050678-1-umesh.nerlige.ramappa@intel.com (mailing list archive)
State New, archived
Headers show
Series i915/perf: Remove code to update PWR_CLK_STATE for gen12 | expand

Commit Message

Umesh Nerlige Ramappa June 29, 2024, 12:56 a.m. UTC 
PWR_CLK_STATE only needs to be modified up until gen11. For gen12 this
code is not applicable. Remove code to update context image with
PWR_CLK_STATE for gen12.

Fixes: 00a7f0d7155c ("drm/i915/tgl: Add perf support on TGL")
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 drivers/gpu/drm/i915/i915_perf.c | 33 --------------------------------
 1 file changed, 33 deletions(-)

Comments

Dixit, Ashutosh June 29, 2024, 1:58 a.m. UTC | #1 
On Fri, 28 Jun 2024 17:56:43 -0700, Umesh Nerlige Ramappa wrote:
>
> PWR_CLK_STATE only needs to be modified up until gen11. For gen12 this
> code is not applicable. Remove code to update context image with
> PWR_CLK_STATE for gen12.
>
> Fixes: 00a7f0d7155c ("drm/i915/tgl: Add perf support on TGL")
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_perf.c | 33 --------------------------------
>  1 file changed, 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 0b1cd4c7a525..025a79fe5920 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -2748,26 +2748,6 @@ oa_configure_all_contexts(struct i915_perf_stream *stream,
>	return 0;
>  }
>
> -static int
> -gen12_configure_all_contexts(struct i915_perf_stream *stream,
> -			     const struct i915_oa_config *oa_config,
> -			     struct i915_active *active)
> -{
> -	struct flex regs[] = {
> -		{
> -			GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),
> -			CTX_R_PWR_CLK_STATE,
> -		},
> -	};
> -
> -	if (stream->engine->class != RENDER_CLASS)
> -		return 0;
> -
> -	return oa_configure_all_contexts(stream,
> -					 regs, ARRAY_SIZE(regs),
> -					 active);
> -}
> -
>  static int
>  lrc_configure_all_contexts(struct i915_perf_stream *stream,
>			   const struct i915_oa_config *oa_config,
> @@ -2874,7 +2854,6 @@ gen12_enable_metric_set(struct i915_perf_stream *stream,
>  {
>	struct drm_i915_private *i915 = stream->perf->i915;
>	struct intel_uncore *uncore = stream->uncore;
> -	struct i915_oa_config *oa_config = stream->oa_config;
>	bool periodic = stream->periodic;
>	u32 period_exponent = stream->period_exponent;
>	u32 sqcnt1;
> @@ -2918,15 +2897,6 @@ gen12_enable_metric_set(struct i915_perf_stream *stream,
>
>	intel_uncore_rmw(uncore, GEN12_SQCNT1, 0, sqcnt1);
>
> -	/*
> -	 * Update all contexts prior writing the mux configurations as we need
> -	 * to make sure all slices/subslices are ON before writing to NOA
> -	 * registers.
> -	 */
> -	ret = gen12_configure_all_contexts(stream, oa_config, active);
> -	if (ret)
> -		return ret;
> -
>	/*
>	 * For Gen12, performance counters are context
>	 * saved/restored. Only enable it for the context that
> @@ -2980,9 +2950,6 @@ static void gen12_disable_metric_set(struct i915_perf_stream *stream)
>				   _MASKED_BIT_DISABLE(GEN12_DISABLE_DOP_GATING));
>	}
>
> -	/* Reset all contexts' slices/subslices configurations. */
> -	gen12_configure_all_contexts(stream, NULL, NULL);
> -
>	/* disable the context save/restore or OAR counters */
>	if (stream->ctx)
>		gen12_configure_oar_context(stream, NULL);
> --
> 2.38.1
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 0b1cd4c7a525..025a79fe5920 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2748,26 +2748,6 @@  oa_configure_all_contexts(struct i915_perf_stream *stream,
 	return 0;
 }
 
-static int
-gen12_configure_all_contexts(struct i915_perf_stream *stream,
-			     const struct i915_oa_config *oa_config,
-			     struct i915_active *active)
-{
-	struct flex regs[] = {
-		{
-			GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),
-			CTX_R_PWR_CLK_STATE,
-		},
-	};
-
-	if (stream->engine->class != RENDER_CLASS)
-		return 0;
-
-	return oa_configure_all_contexts(stream,
-					 regs, ARRAY_SIZE(regs),
-					 active);
-}
-
 static int
 lrc_configure_all_contexts(struct i915_perf_stream *stream,
 			   const struct i915_oa_config *oa_config,
@@ -2874,7 +2854,6 @@  gen12_enable_metric_set(struct i915_perf_stream *stream,
 {
 	struct drm_i915_private *i915 = stream->perf->i915;
 	struct intel_uncore *uncore = stream->uncore;
-	struct i915_oa_config *oa_config = stream->oa_config;
 	bool periodic = stream->periodic;
 	u32 period_exponent = stream->period_exponent;
 	u32 sqcnt1;
@@ -2918,15 +2897,6 @@  gen12_enable_metric_set(struct i915_perf_stream *stream,
 
 	intel_uncore_rmw(uncore, GEN12_SQCNT1, 0, sqcnt1);
 
-	/*
-	 * Update all contexts prior writing the mux configurations as we need
-	 * to make sure all slices/subslices are ON before writing to NOA
-	 * registers.
-	 */
-	ret = gen12_configure_all_contexts(stream, oa_config, active);
-	if (ret)
-		return ret;
-
 	/*
 	 * For Gen12, performance counters are context
 	 * saved/restored. Only enable it for the context that
@@ -2980,9 +2950,6 @@  static void gen12_disable_metric_set(struct i915_perf_stream *stream)
 				   _MASKED_BIT_DISABLE(GEN12_DISABLE_DOP_GATING));
 	}
 
-	/* Reset all contexts' slices/subslices configurations. */
-	gen12_configure_all_contexts(stream, NULL, NULL);
-
 	/* disable the context save/restore or OAR counters */
 	if (stream->ctx)
 		gen12_configure_oar_context(stream, NULL);