| Message ID | 20240705145254.3355-14-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/{i915, xe}: FBC cleanups + tweak fbdev stolen usage | expand |
> -----Original Message----- > From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala > Sent: Friday, July 5, 2024 8:23 PM > To: intel-gfx@lists.freedesktop.org > Cc: intel-xe@lists.freedesktop.org > Subject: [PATCH 13/20] drm/i915/fbc: Extract intel_fbc_cfb_cpp() > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Extract a helper to determine the CFB bytes per pixel value. > Currently this is always 4, but that could change in the future. Looks Good to me. Reviewed-by: Uma Shankar <uma.shankar@intel.com> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_fbc.c | 18 ++++++++++++------ > 1 file changed, 12 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c > b/drivers/gpu/drm/i915/display/intel_fbc.c > index 293e1a3b9a9d..a0e539bc80f1 100644 > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > @@ -140,20 +140,24 @@ static unsigned int intel_fbc_plane_stride(const struct > intel_plane_state *plane > return stride; > } > > +static unsigned int intel_fbc_cfb_cpp(void) { > + return 4; /* FBC always 4 bytes per pixel */ } > + > /* plane stride based cfb stride in bytes, assuming 1:1 compression limit */ static > unsigned int intel_fbc_plane_cfb_stride(const struct intel_plane_state > *plane_state) { > - unsigned int cpp = 4; /* FBC always 4 bytes per pixel */ > + unsigned int cpp = intel_fbc_cfb_cpp(); > > return intel_fbc_plane_stride(plane_state) * cpp; } > > /* minimum acceptable cfb stride in bytes, assuming 1:1 compression limit */ > static unsigned int skl_fbc_min_cfb_stride(struct intel_display *display, > - unsigned int width) > + unsigned int cpp, unsigned int width) > { > unsigned int limit = 4; /* 1:4 compression limit is the worst case */ > - unsigned int cpp = 4; /* FBC always 4 bytes per pixel */ > unsigned int height = 4; /* FBC segment is 4 lines */ > unsigned int stride; > > @@ -179,7 +183,8 @@ static unsigned int skl_fbc_min_cfb_stride(struct > intel_display *display, > > /* properly aligned cfb stride in bytes, assuming 1:1 compression limit */ static > unsigned int _intel_fbc_cfb_stride(struct intel_display *display, > - unsigned int width, unsigned int stride) > + unsigned int cpp, unsigned int width, > + unsigned int stride) > { > /* > * At least some of the platforms require each 4 line segment to @@ - > 187,7 +192,7 @@ static unsigned int _intel_fbc_cfb_stride(struct intel_display > *display, > * that regardless of the compression limit we choose later. > */ > if (DISPLAY_VER(display) >= 9) > - return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(display, > width)); > + return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(display, > cpp, > +width)); > else > return stride; > } > @@ -197,8 +202,9 @@ static unsigned int intel_fbc_cfb_stride(const struct > intel_plane_state *plane_s > struct intel_display *display = to_intel_display(plane_state->uapi.plane- > >dev); > unsigned int stride = intel_fbc_plane_cfb_stride(plane_state); > unsigned int width = drm_rect_width(&plane_state->uapi.src) >> 16; > + unsigned int cpp = intel_fbc_cfb_cpp(); > > - return _intel_fbc_cfb_stride(display, width, stride); > + return _intel_fbc_cfb_stride(display, cpp, width, stride); > } > > /* > -- > 2.44.2
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 293e1a3b9a9d..a0e539bc80f1 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -140,20 +140,24 @@ static unsigned int intel_fbc_plane_stride(const struct intel_plane_state *plane return stride; } +static unsigned int intel_fbc_cfb_cpp(void) +{ + return 4; /* FBC always 4 bytes per pixel */ +} + /* plane stride based cfb stride in bytes, assuming 1:1 compression limit */ static unsigned int intel_fbc_plane_cfb_stride(const struct intel_plane_state *plane_state) { - unsigned int cpp = 4; /* FBC always 4 bytes per pixel */ + unsigned int cpp = intel_fbc_cfb_cpp(); return intel_fbc_plane_stride(plane_state) * cpp; } /* minimum acceptable cfb stride in bytes, assuming 1:1 compression limit */ static unsigned int skl_fbc_min_cfb_stride(struct intel_display *display, - unsigned int width) + unsigned int cpp, unsigned int width) { unsigned int limit = 4; /* 1:4 compression limit is the worst case */ - unsigned int cpp = 4; /* FBC always 4 bytes per pixel */ unsigned int height = 4; /* FBC segment is 4 lines */ unsigned int stride; @@ -179,7 +183,8 @@ static unsigned int skl_fbc_min_cfb_stride(struct intel_display *display, /* properly aligned cfb stride in bytes, assuming 1:1 compression limit */ static unsigned int _intel_fbc_cfb_stride(struct intel_display *display, - unsigned int width, unsigned int stride) + unsigned int cpp, unsigned int width, + unsigned int stride) { /* * At least some of the platforms require each 4 line segment to @@ -187,7 +192,7 @@ static unsigned int _intel_fbc_cfb_stride(struct intel_display *display, * that regardless of the compression limit we choose later. */ if (DISPLAY_VER(display) >= 9) - return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(display, width)); + return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(display, cpp, width)); else return stride; } @@ -197,8 +202,9 @@ static unsigned int intel_fbc_cfb_stride(const struct intel_plane_state *plane_s struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); unsigned int stride = intel_fbc_plane_cfb_stride(plane_state); unsigned int width = drm_rect_width(&plane_state->uapi.src) >> 16; + unsigned int cpp = intel_fbc_cfb_cpp(); - return _intel_fbc_cfb_stride(display, width, stride); + return _intel_fbc_cfb_stride(display, cpp, width, stride); } /*