From patchwork Fri Aug 23 13:08:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13775206 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 06BAAC52D7C for ; Fri, 23 Aug 2024 13:10:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8EFF510E75B; Fri, 23 Aug 2024 13:10:02 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="VTZFdPgL"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by gabe.freedesktop.org (Postfix) with ESMTPS id EA03910E791; Fri, 23 Aug 2024 13:10:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724418602; x=1755954602; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RZXagvd9a/iXlh5duGIJn7XPRJeVbbKXDz7sy800Ifs=; b=VTZFdPgLQS2rC275po5UoX/Exufod/Vdc1J5ANcGRjgGLHhzpFH7CUGd GnvNtJ0PIFvoX1myb7UHRLHIoHcEuYgFy166DCmxDcDdGaw0UCNAfGOMA FqBiKPncUk516PZVABTeUFAjkNPID8jXHtYFYo9bg/K3BhcZNFih6axzh 45TCblhDRGsARdaqYNQ6aEfeJHRMRGsfc6u+IcSRQrE4tbyCb+tO3aqIo ISqa4KPEOEPZy8ZNqXOzvpUhhyNiyi0KgyXQVXmVCsB14SqpopG28AtDQ yCpqGnNSGoaKhWH8fcTOwep+jDCHrAsY5sneXiT+T9TDnaAxr3Sn4tqEc A==; X-CSE-ConnectionGUID: GFtrMnUFTwSxggLoZ2t8uA== X-CSE-MsgGUID: ZiGsqURTRkSj5qj5ysf6gg== X-IronPort-AV: E=McAfee;i="6700,10204,11172"; a="22483327" X-IronPort-AV: E=Sophos;i="6.10,170,1719903600"; d="scan'208";a="22483327" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Aug 2024 06:10:02 -0700 X-CSE-ConnectionGUID: 3gNkFhfYTRaoiKpOmn23nw== X-CSE-MsgGUID: Q4DF+EcSQJ+sbOV/AG3HdQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,170,1719903600"; d="scan'208";a="66614421" Received: from mwiniars-desk2.ger.corp.intel.com (HELO intel.com) ([10.245.246.236]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Aug 2024 06:09:59 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Chris Wilson , Tvrtko Ursulin , Andi Shyti Subject: [PATCH v3 08/15] drm/i915/gt: Remove cslices mask value from the CCS structure Date: Fri, 23 Aug 2024 15:08:48 +0200 Message-ID: <20240823130855.72436-9-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240823130855.72436-1-andi.shyti@linux.intel.com> References: <20240823130855.72436-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Following the decision to manage CCS engine creation within UABI engines, the "cslices" variable in the "ccs" structure in the "gt" is no longer needed. Remove it is now redundant. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt_types.h | 5 ----- 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c index a6c33b471567..fc8a23fc28b6 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c @@ -9,7 +9,7 @@ static void intel_gt_apply_ccs_mode(struct intel_gt *gt) { - unsigned long cslices_mask = gt->ccs.cslices; + unsigned long cslices_mask = CCS_MASK(gt); u32 mode_val = 0; /* CCS engine id, i.e. the engines position in the engine's bitmask */ int engine; diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index 9e257f34d05b..71e43071da0b 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -218,11 +218,6 @@ struct intel_gt { * i.e. how the CCS streams are distributed amongs the slices. */ struct { - /* - * Mask of the non fused CCS slices - * to be used for the load balancing - */ - intel_engine_mask_t cslices; u32 mode_reg_val; } ccs;