diff mbox series

[v6,1/2] drm/i915/display: Plane capability for 64k phys alignment

Message ID 20240826170117.327709-2-maarten.lankhorst@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series drm/xe: Align all VRAM scanout buffers to 64k physical pages when needed. | expand

Commit Message

Maarten Lankhorst Aug. 26, 2024, 5:01 p.m. UTC
Some plane formats have been designed to require 64k physical alignment.
By returning whether this is the case for certain formats, we do not
need to hardcode this check inside Xe.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fb.c | 20 +++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_fb.h |  2 ++
 2 files changed, 21 insertions(+), 1 deletion(-)

Comments

Rodrigo Vivi Aug. 27, 2024, 4:26 p.m. UTC | #1
On Mon, Aug 26, 2024 at 07:01:15PM +0200, Maarten Lankhorst wrote:
> Some plane formats have been designed to require 64k physical alignment.
> By returning whether this is the case for certain formats, we do not
> need to hardcode this check inside Xe.
> 
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>

Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

I still believe that 'CAPS' 'needs64k' is strange. But this is indeed
the cleanest way we found and easy to port to future platforms.

Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
to get this merged through drm-xe-next as well where this is
needed right now.

> ---
>  drivers/gpu/drm/i915/display/intel_fb.c | 20 +++++++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_fb.h |  2 ++
>  2 files changed, 21 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> index d2716915d046d..5be7bb43e2e0d 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -169,7 +169,7 @@ static const struct intel_modifier_desc intel_modifiers[] = {
>  	}, {
>  		.modifier = I915_FORMAT_MOD_4_TILED_BMG_CCS,
>  		.display_ver = { 14, -1 },
> -		.plane_caps = INTEL_PLANE_CAP_TILING_4,
> +		.plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_NEED64K_PHYS,
>  	}, {
>  		.modifier = I915_FORMAT_MOD_4_TILED_MTL_MC_CCS,
>  		.display_ver = { 14, 14 },
> @@ -420,6 +420,24 @@ bool intel_fb_is_mc_ccs_modifier(u64 modifier)
>  				      INTEL_PLANE_CAP_CCS_MC);
>  }
>  
> +/**
> + * intel_fb_needs_64k_phys: Check if modifier requires 64k physical placement.
> + * @modifier: Modifier to check
> + *
> + * Returns:
> + * Returns %true if @modifier requires 64k aligned physical pages.
> + */
> +bool intel_fb_needs_64k_phys(u64 modifier)
> +{
> +	const struct intel_modifier_desc *md = lookup_modifier_or_null(modifier);
> +
> +	if (!md)
> +		return false;
> +
> +	return plane_caps_contain_any(md->plane_caps,
> +				      INTEL_PLANE_CAP_NEED64K_PHYS);
> +}
> +
>  static bool check_modifier_display_ver_range(const struct intel_modifier_desc *md,
>  					     u8 display_ver_from, u8 display_ver_until)
>  {
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h
> index 6dee0c8b7f226..10de437e8ef84 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.h
> +++ b/drivers/gpu/drm/i915/display/intel_fb.h
> @@ -28,11 +28,13 @@ struct intel_plane_state;
>  #define INTEL_PLANE_CAP_TILING_Y	BIT(4)
>  #define INTEL_PLANE_CAP_TILING_Yf	BIT(5)
>  #define INTEL_PLANE_CAP_TILING_4	BIT(6)
> +#define INTEL_PLANE_CAP_NEED64K_PHYS	BIT(7)
>  
>  bool intel_fb_is_tiled_modifier(u64 modifier);
>  bool intel_fb_is_ccs_modifier(u64 modifier);
>  bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier);
>  bool intel_fb_is_mc_ccs_modifier(u64 modifier);
> +bool intel_fb_needs_64k_phys(u64 modifier);
>  
>  bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane);
>  int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb);
> -- 
> 2.45.2
>
Rodrigo Vivi Aug. 27, 2024, 6:59 p.m. UTC | #2
On Tue, Aug 27, 2024 at 12:26:46PM -0400, Rodrigo Vivi wrote:
> On Mon, Aug 26, 2024 at 07:01:15PM +0200, Maarten Lankhorst wrote:
> > Some plane formats have been designed to require 64k physical alignment.
> > By returning whether this is the case for certain formats, we do not
> > need to hardcode this check inside Xe.
> > 
> > Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> 
> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> I still believe that 'CAPS' 'needs64k' is strange. But this is indeed
> the cleanest way we found and easy to port to future platforms.
> 
> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> to get this merged through drm-xe-next as well where this is
> needed right now.

Since it is display only and would depend on
 commit fca0abb23447 ("drm/i915/display: allow creation of Xe2 ccs framebuffers")
to apply cleanly and this commit is only part of drm-intel-next yet,
I went ahead and did the other way around and push both patches,
including the Xe one into drm-intel-next.

> 
> > ---
> >  drivers/gpu/drm/i915/display/intel_fb.c | 20 +++++++++++++++++++-
> >  drivers/gpu/drm/i915/display/intel_fb.h |  2 ++
> >  2 files changed, 21 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> > index d2716915d046d..5be7bb43e2e0d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > @@ -169,7 +169,7 @@ static const struct intel_modifier_desc intel_modifiers[] = {
> >  	}, {
> >  		.modifier = I915_FORMAT_MOD_4_TILED_BMG_CCS,
> >  		.display_ver = { 14, -1 },
> > -		.plane_caps = INTEL_PLANE_CAP_TILING_4,
> > +		.plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_NEED64K_PHYS,
> >  	}, {
> >  		.modifier = I915_FORMAT_MOD_4_TILED_MTL_MC_CCS,
> >  		.display_ver = { 14, 14 },
> > @@ -420,6 +420,24 @@ bool intel_fb_is_mc_ccs_modifier(u64 modifier)
> >  				      INTEL_PLANE_CAP_CCS_MC);
> >  }
> >  
> > +/**
> > + * intel_fb_needs_64k_phys: Check if modifier requires 64k physical placement.
> > + * @modifier: Modifier to check
> > + *
> > + * Returns:
> > + * Returns %true if @modifier requires 64k aligned physical pages.
> > + */
> > +bool intel_fb_needs_64k_phys(u64 modifier)
> > +{
> > +	const struct intel_modifier_desc *md = lookup_modifier_or_null(modifier);
> > +
> > +	if (!md)
> > +		return false;
> > +
> > +	return plane_caps_contain_any(md->plane_caps,
> > +				      INTEL_PLANE_CAP_NEED64K_PHYS);
> > +}
> > +
> >  static bool check_modifier_display_ver_range(const struct intel_modifier_desc *md,
> >  					     u8 display_ver_from, u8 display_ver_until)
> >  {
> > diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h
> > index 6dee0c8b7f226..10de437e8ef84 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fb.h
> > +++ b/drivers/gpu/drm/i915/display/intel_fb.h
> > @@ -28,11 +28,13 @@ struct intel_plane_state;
> >  #define INTEL_PLANE_CAP_TILING_Y	BIT(4)
> >  #define INTEL_PLANE_CAP_TILING_Yf	BIT(5)
> >  #define INTEL_PLANE_CAP_TILING_4	BIT(6)
> > +#define INTEL_PLANE_CAP_NEED64K_PHYS	BIT(7)
> >  
> >  bool intel_fb_is_tiled_modifier(u64 modifier);
> >  bool intel_fb_is_ccs_modifier(u64 modifier);
> >  bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier);
> >  bool intel_fb_is_mc_ccs_modifier(u64 modifier);
> > +bool intel_fb_needs_64k_phys(u64 modifier);
> >  
> >  bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane);
> >  int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb);
> > -- 
> > 2.45.2
> >
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index d2716915d046d..5be7bb43e2e0d 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -169,7 +169,7 @@  static const struct intel_modifier_desc intel_modifiers[] = {
 	}, {
 		.modifier = I915_FORMAT_MOD_4_TILED_BMG_CCS,
 		.display_ver = { 14, -1 },
-		.plane_caps = INTEL_PLANE_CAP_TILING_4,
+		.plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_NEED64K_PHYS,
 	}, {
 		.modifier = I915_FORMAT_MOD_4_TILED_MTL_MC_CCS,
 		.display_ver = { 14, 14 },
@@ -420,6 +420,24 @@  bool intel_fb_is_mc_ccs_modifier(u64 modifier)
 				      INTEL_PLANE_CAP_CCS_MC);
 }
 
+/**
+ * intel_fb_needs_64k_phys: Check if modifier requires 64k physical placement.
+ * @modifier: Modifier to check
+ *
+ * Returns:
+ * Returns %true if @modifier requires 64k aligned physical pages.
+ */
+bool intel_fb_needs_64k_phys(u64 modifier)
+{
+	const struct intel_modifier_desc *md = lookup_modifier_or_null(modifier);
+
+	if (!md)
+		return false;
+
+	return plane_caps_contain_any(md->plane_caps,
+				      INTEL_PLANE_CAP_NEED64K_PHYS);
+}
+
 static bool check_modifier_display_ver_range(const struct intel_modifier_desc *md,
 					     u8 display_ver_from, u8 display_ver_until)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h
index 6dee0c8b7f226..10de437e8ef84 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -28,11 +28,13 @@  struct intel_plane_state;
 #define INTEL_PLANE_CAP_TILING_Y	BIT(4)
 #define INTEL_PLANE_CAP_TILING_Yf	BIT(5)
 #define INTEL_PLANE_CAP_TILING_4	BIT(6)
+#define INTEL_PLANE_CAP_NEED64K_PHYS	BIT(7)
 
 bool intel_fb_is_tiled_modifier(u64 modifier);
 bool intel_fb_is_ccs_modifier(u64 modifier);
 bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier);
 bool intel_fb_is_mc_ccs_modifier(u64 modifier);
+bool intel_fb_needs_64k_phys(u64 modifier);
 
 bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane);
 int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb);