| Message ID | 20240926064759.1313335-3-jouni.hogander@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Implement Wa 14019834836 | expand |
> -----Original Message----- > From: Hogander, Jouni <jouni.hogander@intel.com> > Sent: Thursday, 26 September 2024 9.48 > To: intel-gfx@lists.freedesktop.org > Cc: Kahola, Mika <mika.kahola@intel.com>; Sousa, Gustavo > <gustavo.sousa@intel.com>; Hogander, Jouni <jouni.hogander@intel.com> > Subject: [PATCH v2 2/2] drm/i915/psr: Implement Wa 14019834836 > > This patch implements HW workaround 14019834836 for display version 30. > > v2: > - move Wa 14019834836 to it's own function > - apply only for display version 30 > Looks ok to me. Reviewed-by: Mika Kahola <mika.kahola@intel.com> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 36 ++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index f3db0f997ef31..eaa3dd40efc9e 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -2611,6 +2611,38 @@ static bool > psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *c > return true; > } > > +/* Wa 14019834836 */ > +static void intel_psr_apply_pr_link_on_su_wa(struct intel_crtc_state > +*crtc_state) { > + struct intel_display *display = to_intel_display(crtc_state); > + struct intel_encoder *encoder; > + int hactive_limit; > + > + if (crtc_state->psr2_su_area.y1 != 0 || > + crtc_state->psr2_su_area.y2 != 0) > + return; > + > + if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) > + hactive_limit = intel_dp_is_uhbr(crtc_state) ? 1230 : 546; > + else > + hactive_limit = intel_dp_is_uhbr(crtc_state) ? 615 : 273; > + > + if (crtc_state->hw.adjusted_mode.hdisplay < hactive_limit) > + return; > + > + for_each_intel_encoder_mask_with_psr(display->drm, encoder, > + crtc_state->uapi.encoder_mask) { > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > + > + if (!intel_dp_is_edp(intel_dp) && > + intel_dp->psr.panel_replay_enabled && > + intel_dp->psr.sel_update_enabled) { > + crtc_state->psr2_su_area.y2++; > + return; > + } > + } > +} > + > static void > intel_psr_apply_su_area_workarounds(struct intel_crtc_state *crtc_state) { > @@ -2623,6 +2655,10 @@ intel_psr_apply_su_area_workarounds(struct > intel_crtc_state *crtc_state) > IS_ALDERLAKE_P(i915) || IS_TIGERLAKE(i915))) && > crtc_state->splitter.enable) > crtc_state->psr2_su_area.y1 = 0; > + > + /* Wa 14019834836 */ > + if (DISPLAY_VER(display) == 30) > + intel_psr_apply_pr_link_on_su_wa(crtc_state); > } > > int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, > -- > 2.34.1
On Wed, 2024-10-02 at 12:04 +0000, Kahola, Mika wrote: > > -----Original Message----- > > From: Hogander, Jouni <jouni.hogander@intel.com> > > Sent: Thursday, 26 September 2024 9.48 > > To: intel-gfx@lists.freedesktop.org > > Cc: Kahola, Mika <mika.kahola@intel.com>; Sousa, Gustavo > > <gustavo.sousa@intel.com>; Hogander, Jouni > > <jouni.hogander@intel.com> > > Subject: [PATCH v2 2/2] drm/i915/psr: Implement Wa 14019834836 > > > > This patch implements HW workaround 14019834836 for display version > > 30. > > > > v2: > > - move Wa 14019834836 to it's own function > > - apply only for display version 30 > > > > Looks ok to me. > > Reviewed-by: Mika Kahola <mika.kahola@intel.com> Thank you Mika and Gustavo for reviewing my patches. These are now pushed to drm-intel-next. BR, Jouni Högander > > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_psr.c | 36 > > ++++++++++++++++++++++++ > > 1 file changed, 36 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > b/drivers/gpu/drm/i915/display/intel_psr.c > > index f3db0f997ef31..eaa3dd40efc9e 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > @@ -2611,6 +2611,38 @@ static bool > > psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state > > *c > > return true; > > } > > > > +/* Wa 14019834836 */ > > +static void intel_psr_apply_pr_link_on_su_wa(struct > > intel_crtc_state > > +*crtc_state) { > > + struct intel_display *display = > > to_intel_display(crtc_state); > > + struct intel_encoder *encoder; > > + int hactive_limit; > > + > > + if (crtc_state->psr2_su_area.y1 != 0 || > > + crtc_state->psr2_su_area.y2 != 0) > > + return; > > + > > + if (crtc_state->output_format == > > INTEL_OUTPUT_FORMAT_YCBCR420) > > + hactive_limit = intel_dp_is_uhbr(crtc_state) ? 1230 > > : 546; > > + else > > + hactive_limit = intel_dp_is_uhbr(crtc_state) ? 615 > > : 273; > > + > > + if (crtc_state->hw.adjusted_mode.hdisplay < hactive_limit) > > + return; > > + > > + for_each_intel_encoder_mask_with_psr(display->drm, encoder, > > + crtc_state- > > >uapi.encoder_mask) { > > + struct intel_dp *intel_dp = > > enc_to_intel_dp(encoder); > > + > > + if (!intel_dp_is_edp(intel_dp) && > > + intel_dp->psr.panel_replay_enabled && > > + intel_dp->psr.sel_update_enabled) { > > + crtc_state->psr2_su_area.y2++; > > + return; > > + } > > + } > > +} > > + > > static void > > intel_psr_apply_su_area_workarounds(struct intel_crtc_state > > *crtc_state) { > > @@ -2623,6 +2655,10 @@ intel_psr_apply_su_area_workarounds(struct > > intel_crtc_state *crtc_state) > > IS_ALDERLAKE_P(i915) || IS_TIGERLAKE(i915))) && > > crtc_state->splitter.enable) > > crtc_state->psr2_su_area.y1 = 0; > > + > > + /* Wa 14019834836 */ > > + if (DISPLAY_VER(display) == 30) > > + intel_psr_apply_pr_link_on_su_wa(crtc_state); > > } > > > > int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, > > -- > > 2.34.1 >
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index f3db0f997ef31..eaa3dd40efc9e 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2611,6 +2611,38 @@ static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *c return true; } +/* Wa 14019834836 */ +static void intel_psr_apply_pr_link_on_su_wa(struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + struct intel_encoder *encoder; + int hactive_limit; + + if (crtc_state->psr2_su_area.y1 != 0 || + crtc_state->psr2_su_area.y2 != 0) + return; + + if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) + hactive_limit = intel_dp_is_uhbr(crtc_state) ? 1230 : 546; + else + hactive_limit = intel_dp_is_uhbr(crtc_state) ? 615 : 273; + + if (crtc_state->hw.adjusted_mode.hdisplay < hactive_limit) + return; + + for_each_intel_encoder_mask_with_psr(display->drm, encoder, + crtc_state->uapi.encoder_mask) { + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + + if (!intel_dp_is_edp(intel_dp) && + intel_dp->psr.panel_replay_enabled && + intel_dp->psr.sel_update_enabled) { + crtc_state->psr2_su_area.y2++; + return; + } + } +} + static void intel_psr_apply_su_area_workarounds(struct intel_crtc_state *crtc_state) { @@ -2623,6 +2655,10 @@ intel_psr_apply_su_area_workarounds(struct intel_crtc_state *crtc_state) IS_ALDERLAKE_P(i915) || IS_TIGERLAKE(i915))) && crtc_state->splitter.enable) crtc_state->psr2_su_area.y1 = 0; + + /* Wa 14019834836 */ + if (DISPLAY_VER(display) == 30) + intel_psr_apply_pr_link_on_su_wa(crtc_state); } int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
This patch implements HW workaround 14019834836 for display version 30. v2: - move Wa 14019834836 to it's own function - apply only for display version 30 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 36 ++++++++++++++++++++++++ 1 file changed, 36 insertions(+)