| Message ID | 20241009084634.1801800-1-suraj.kandpal@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/cdclk: Check cdclk value before division | expand |
On Wed, Oct 09, 2024 at 02:16:34PM +0530, Suraj Kandpal wrote: > Check cdclk value to avoid a divide by zero error. Since > bxt_cdclk_init_hw has cdclk can end up being 0 and then > we have a call to bxt_set_cdclk where we may end up dividing > this value by 0. Not possible unless someone completely screwed the cdclk tables and/or refclk readout, in which case oops seems like a perfectly reasonable outcome to me. > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c > index fa1c2012b10c..a5acc70fb87c 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -1921,7 +1921,7 @@ static u32 xe2lpd_mdclk_source_sel(struct intel_display *display) > int intel_mdclk_cdclk_ratio(struct intel_display *display, > const struct intel_cdclk_config *cdclk_config) > { > - if (mdclk_source_is_cdclk_pll(display)) > + if (mdclk_source_is_cdclk_pll(display) && cdclk_config->cdclk) > return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk); > > /* Otherwise, source for MDCLK is CD2XCLK. */ > -- > 2.43.2
> -----Original Message----- > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > Sent: Wednesday, October 9, 2024 2:32 PM > To: Kandpal, Suraj <suraj.kandpal@intel.com> > Cc: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; Shankar, > Uma <uma.shankar@intel.com>; Borah, Chaitanya Kumar > <chaitanya.kumar.borah@intel.com> > Subject: Re: [PATCH] drm/i915/cdclk: Check cdclk value before division > > On Wed, Oct 09, 2024 at 02:16:34PM +0530, Suraj Kandpal wrote: > > Check cdclk value to avoid a divide by zero error. Since > > bxt_cdclk_init_hw has cdclk can end up being 0 and then we have a call > > to bxt_set_cdclk where we may end up dividing this value by 0. > > Not possible unless someone completely screwed the cdclk tables and/or > refclk readout, in which case oops seems like a perfectly reasonable > outcome to me. Ohkay got it > > > > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c > > b/drivers/gpu/drm/i915/display/intel_cdclk.c > > index fa1c2012b10c..a5acc70fb87c 100644 > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > > @@ -1921,7 +1921,7 @@ static u32 xe2lpd_mdclk_source_sel(struct > > intel_display *display) int intel_mdclk_cdclk_ratio(struct intel_display > *display, > > const struct intel_cdclk_config *cdclk_config) { > > - if (mdclk_source_is_cdclk_pll(display)) > > + if (mdclk_source_is_cdclk_pll(display) && cdclk_config->cdclk) > > return DIV_ROUND_UP(cdclk_config->vco, cdclk_config- > >cdclk); > > > > /* Otherwise, source for MDCLK is CD2XCLK. */ > > -- > > 2.43.2 > > -- > Ville Syrjälä > Intel
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index fa1c2012b10c..a5acc70fb87c 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1921,7 +1921,7 @@ static u32 xe2lpd_mdclk_source_sel(struct intel_display *display) int intel_mdclk_cdclk_ratio(struct intel_display *display, const struct intel_cdclk_config *cdclk_config) { - if (mdclk_source_is_cdclk_pll(display)) + if (mdclk_source_is_cdclk_pll(display) && cdclk_config->cdclk) return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk); /* Otherwise, source for MDCLK is CD2XCLK. */
Check cdclk value to avoid a divide by zero error. Since bxt_cdclk_init_hw has cdclk can end up being 0 and then we have a call to bxt_set_cdclk where we may end up dividing this value by 0. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> --- drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)