From patchwork Wed Oct 9 18:22:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13829059 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 14641CEE33B for ; Wed, 9 Oct 2024 18:22:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9E7DF10E7B3; Wed, 9 Oct 2024 18:22:16 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Cy7g59xS"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id EE11E10E7B3 for ; Wed, 9 Oct 2024 18:22:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728498136; x=1760034136; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=4KlXhi8vTYMQPzobaYyNJ3qbMBRK9eI0CLC3urk4vOo=; b=Cy7g59xSnCWOsHuvQkZ2KN1wtGV/0iZ6rx+j5d6Q/MCnG9wDxASRaTaA 4hkG4l0s8eQefjpXskC/fESIhMuaUSrJhga5I8XW9oBvxgWrsv4NhXuO8 fnkY5cYU1yge8QJ33j9TtkrUKOFNixJC8iPCkzIqGWdrgCUFGTx+MOsea IyvmsHUTDflhg49NzUgsFMiZPRBXhUWWy625KaaDSVERpIcj7aOW9h3Na iOjLyTKfCyQRP/J1Z7E88P69lJUXE+bCgP/bmIfYGAx36yohRgF10GMj9 8BfZAHKCRHUqd77gWpTPwzqQbP9ZQAipdlkjm/7CC3pjclmbay3jymH5T w==; X-CSE-ConnectionGUID: iyMS0RMmSOq67L0BRPX8Yw== X-CSE-MsgGUID: Djj0CjqkRBubjnFPb9LUIQ== X-IronPort-AV: E=McAfee;i="6700,10204,11220"; a="15438994" X-IronPort-AV: E=Sophos;i="6.11,190,1725346800"; d="scan'208";a="15438994" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Oct 2024 11:22:16 -0700 X-CSE-ConnectionGUID: X21JThZsTR6lhGf/INkoUA== X-CSE-MsgGUID: GIEIFe7dQZ2Wnm28K/R5kg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,190,1725346800"; d="scan'208";a="76430363" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 09 Oct 2024 11:22:15 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 09 Oct 2024 21:22:13 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 2/9] drm/i915: Allow async flips with compression on ICL Date: Wed, 9 Oct 2024 21:22:00 +0300 Message-ID: <20241009182207.22900-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241009182207.22900-1-ville.syrjala@linux.intel.com> References: <20241009182207.22900-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Apparently ICL can do async flips with CCS. In fact it already seems to work on GLK, but apparently can lead to underruns there so we'll only enable it for ICL. Signed-off-by: Ville Syrjälä Reviewed-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_display.c | 21 +++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 21d412b158e8..70a5e5357a14 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -6507,7 +6507,26 @@ static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct in return -EINVAL; } break; - + case I915_FORMAT_MOD_Y_TILED_CCS: + case I915_FORMAT_MOD_Yf_TILED_CCS: + /* + * Display WA #0731: skl + * WaDisableRCWithAsyncFlip: skl + * "When render decompression is enabled, hardware + * internally converts the Async flips to Sync flips." + * + * Display WA #1159: glk + * "Async flip with render compression may result in + * intermittent underrun corruption." + */ + if (DISPLAY_VER(i915) < 11) { + drm_dbg_kms(&i915->drm, + "[PLANE:%d:%s] Modifier 0x%llx does not support async flip on display ver %d\n", + plane->base.base.id, plane->base.name, + new_plane_state->hw.fb->modifier, DISPLAY_VER(i915)); + return -EINVAL; + } + break; case I915_FORMAT_MOD_X_TILED: case I915_FORMAT_MOD_Y_TILED: case I915_FORMAT_MOD_Yf_TILED: