| Message ID | 20241010224311.50133-7-matthew.s.atwood@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add xe3lpd edp enabling | expand |
On Thu, 10 Oct 2024, Matt Atwood <matthew.s.atwood@intel.com> wrote: > From: Suraj Kandpal <suraj.kandpal@intel.com> > > hblank restriction now includes all of xe3. > > v2: add additional definition instead of function, commit message typo > fix and update. > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> > --- > drivers/gpu/drm/i915/display/intel_hdcp.c | 5 +++-- > drivers/gpu/drm/i915/i915_reg.h | 1 + > 2 files changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c > index ed6aa87403e2..46d5019499a8 100644 > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c > @@ -47,10 +47,11 @@ intel_hdcp_disable_hdcp_line_rekeying(struct intel_encoder *encoder, > intel_de_rmw(display, MTL_CHICKEN_TRANS(hdcp->cpu_transcoder), > 0, HDCP_LINE_REKEY_DISABLE); > else if (IS_DISPLAY_VER_STEP(display, IP_VER(14, 1), STEP_B0, STEP_FOREVER) || > - IS_DISPLAY_VER_STEP(display, IP_VER(20, 0), STEP_B0, STEP_FOREVER)) > + IS_DISPLAY_VER_STEP(display, IP_VER(20, 0), STEP_B0, STEP_FOREVER) || > + DISPLAY_VER(display) >= 30) > intel_de_rmw(display, > TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder), > - 0, TRANS_DDI_HDCP_LINE_REKEY_DISABLE); > + 0, XE3_TRANS_DDI_HDCP_LINE_REKEY_DISABLE); This now uses bit 15 also for display version < 30. > } > } > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index d30459f8d1cb..fc30e0056b07 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3833,6 +3833,7 @@ enum skl_power_gate { > #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12) > #define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12) > #define TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(12) > +#define XE3_TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(15) > #define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10) > #define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \ > REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index ed6aa87403e2..46d5019499a8 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -47,10 +47,11 @@ intel_hdcp_disable_hdcp_line_rekeying(struct intel_encoder *encoder, intel_de_rmw(display, MTL_CHICKEN_TRANS(hdcp->cpu_transcoder), 0, HDCP_LINE_REKEY_DISABLE); else if (IS_DISPLAY_VER_STEP(display, IP_VER(14, 1), STEP_B0, STEP_FOREVER) || - IS_DISPLAY_VER_STEP(display, IP_VER(20, 0), STEP_B0, STEP_FOREVER)) + IS_DISPLAY_VER_STEP(display, IP_VER(20, 0), STEP_B0, STEP_FOREVER) || + DISPLAY_VER(display) >= 30) intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder), - 0, TRANS_DDI_HDCP_LINE_REKEY_DISABLE); + 0, XE3_TRANS_DDI_HDCP_LINE_REKEY_DISABLE); } } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d30459f8d1cb..fc30e0056b07 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3833,6 +3833,7 @@ enum skl_power_gate { #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12) #define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12) #define TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(12) +#define XE3_TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(15) #define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10) #define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \ REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)