diff mbox series

[v2,1/4] drm/i915/pciids: Refactor DG2 PCI IDs into workaround ranges

Message ID 20241011103250.1035316-2-raag.jadav@intel.com (mailing list archive)
State New, archived
Headers show
Series Implement Wa_14022698537 | expand

Commit Message

Raag Jadav Oct. 11, 2024, 10:32 a.m. UTC
Refactor DG2 PCI IDs into device ranges that will be used in a workaround.

Signed-off-by: Raag Jadav <raag.jadav@intel.com>
---
 include/drm/intel/i915_pciids.h | 34 +++++++++++++++++++++++----------
 1 file changed, 24 insertions(+), 10 deletions(-)

Comments

Jani Nikula Oct. 11, 2024, 10:40 a.m. UTC | #1
On Fri, 11 Oct 2024, Raag Jadav <raag.jadav@intel.com> wrote:
> Refactor DG2 PCI IDs into device ranges that will be used in a workaround.

Give the PCI ID ranges a name other than "WA". What are they?

BR,
Jani.

>
> Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> ---
>  include/drm/intel/i915_pciids.h | 34 +++++++++++++++++++++++----------
>  1 file changed, 24 insertions(+), 10 deletions(-)
>
> diff --git a/include/drm/intel/i915_pciids.h b/include/drm/intel/i915_pciids.h
> index 2bf03ebfcf73..82f960f625c7 100644
> --- a/include/drm/intel/i915_pciids.h
> +++ b/include/drm/intel/i915_pciids.h
> @@ -724,37 +724,51 @@
>  	MACRO__(0xA7AB, ## __VA_ARGS__)
>  
>  /* DG2 */
> +#define INTEL_DG2_G10_WA_IDS(MACRO__, ...) \
> +	MACRO__(0x56A0, ## __VA_ARGS__), \
> +	MACRO__(0x56A1, ## __VA_ARGS__), \
> +	MACRO__(0x56A2, ## __VA_ARGS__)
> +
>  #define INTEL_DG2_G10_IDS(MACRO__, ...) \
> +	INTEL_DG2_G10_WA_IDS(MACRO__, ## __VA_ARGS__), \
>  	MACRO__(0x5690, ## __VA_ARGS__), \
>  	MACRO__(0x5691, ## __VA_ARGS__), \
>  	MACRO__(0x5692, ## __VA_ARGS__), \
> -	MACRO__(0x56A0, ## __VA_ARGS__), \
> -	MACRO__(0x56A1, ## __VA_ARGS__), \
> -	MACRO__(0x56A2, ## __VA_ARGS__), \
>  	MACRO__(0x56BE, ## __VA_ARGS__), \
>  	MACRO__(0x56BF, ## __VA_ARGS__)
>  
> +#define INTEL_DG2_G11_WA_IDS(MACRO__, ...) \
> +	MACRO__(0x56A5, ## __VA_ARGS__), \
> +	MACRO__(0x56A6, ## __VA_ARGS__), \
> +	MACRO__(0x56B0, ## __VA_ARGS__), \
> +	MACRO__(0x56B1, ## __VA_ARGS__)
> +
>  #define INTEL_DG2_G11_IDS(MACRO__, ...) \
> +	INTEL_DG2_G11_WA_IDS(MACRO__, ## __VA_ARGS__), \
>  	MACRO__(0x5693, ## __VA_ARGS__), \
>  	MACRO__(0x5694, ## __VA_ARGS__), \
>  	MACRO__(0x5695, ## __VA_ARGS__), \
> -	MACRO__(0x56A5, ## __VA_ARGS__), \
> -	MACRO__(0x56A6, ## __VA_ARGS__), \
> -	MACRO__(0x56B0, ## __VA_ARGS__), \
> -	MACRO__(0x56B1, ## __VA_ARGS__), \
>  	MACRO__(0x56BA, ## __VA_ARGS__), \
>  	MACRO__(0x56BB, ## __VA_ARGS__), \
>  	MACRO__(0x56BC, ## __VA_ARGS__), \
>  	MACRO__(0x56BD, ## __VA_ARGS__)
>  
> -#define INTEL_DG2_G12_IDS(MACRO__, ...) \
> -	MACRO__(0x5696, ## __VA_ARGS__), \
> -	MACRO__(0x5697, ## __VA_ARGS__), \
> +#define INTEL_DG2_G12_WA_IDS(MACRO__, ...) \
>  	MACRO__(0x56A3, ## __VA_ARGS__), \
>  	MACRO__(0x56A4, ## __VA_ARGS__), \
>  	MACRO__(0x56B2, ## __VA_ARGS__), \
>  	MACRO__(0x56B3, ## __VA_ARGS__)
>  
> +#define INTEL_DG2_G12_IDS(MACRO__, ...) \
> +	INTEL_DG2_G11_WA_IDS(MACRO__, ## __VA_ARGS__), \
> +	MACRO__(0x5696, ## __VA_ARGS__), \
> +	MACRO__(0x5697, ## __VA_ARGS__)
> +
> +#define INTEL_DG2_WA_IDS(MACRO__, ...) \
> +	INTEL_DG2_G10_WA_IDS(MACRO__, ## __VA_ARGS__), \
> +	INTEL_DG2_G11_WA_IDS(MACRO__, ## __VA_ARGS__), \
> +	INTEL_DG2_G12_WA_IDS(MACRO__, ## __VA_ARGS__)
> +
>  #define INTEL_DG2_IDS(MACRO__, ...) \
>  	INTEL_DG2_G10_IDS(MACRO__, ## __VA_ARGS__), \
>  	INTEL_DG2_G11_IDS(MACRO__, ## __VA_ARGS__), \
diff mbox series

Patch

diff --git a/include/drm/intel/i915_pciids.h b/include/drm/intel/i915_pciids.h
index 2bf03ebfcf73..82f960f625c7 100644
--- a/include/drm/intel/i915_pciids.h
+++ b/include/drm/intel/i915_pciids.h
@@ -724,37 +724,51 @@ 
 	MACRO__(0xA7AB, ## __VA_ARGS__)
 
 /* DG2 */
+#define INTEL_DG2_G10_WA_IDS(MACRO__, ...) \
+	MACRO__(0x56A0, ## __VA_ARGS__), \
+	MACRO__(0x56A1, ## __VA_ARGS__), \
+	MACRO__(0x56A2, ## __VA_ARGS__)
+
 #define INTEL_DG2_G10_IDS(MACRO__, ...) \
+	INTEL_DG2_G10_WA_IDS(MACRO__, ## __VA_ARGS__), \
 	MACRO__(0x5690, ## __VA_ARGS__), \
 	MACRO__(0x5691, ## __VA_ARGS__), \
 	MACRO__(0x5692, ## __VA_ARGS__), \
-	MACRO__(0x56A0, ## __VA_ARGS__), \
-	MACRO__(0x56A1, ## __VA_ARGS__), \
-	MACRO__(0x56A2, ## __VA_ARGS__), \
 	MACRO__(0x56BE, ## __VA_ARGS__), \
 	MACRO__(0x56BF, ## __VA_ARGS__)
 
+#define INTEL_DG2_G11_WA_IDS(MACRO__, ...) \
+	MACRO__(0x56A5, ## __VA_ARGS__), \
+	MACRO__(0x56A6, ## __VA_ARGS__), \
+	MACRO__(0x56B0, ## __VA_ARGS__), \
+	MACRO__(0x56B1, ## __VA_ARGS__)
+
 #define INTEL_DG2_G11_IDS(MACRO__, ...) \
+	INTEL_DG2_G11_WA_IDS(MACRO__, ## __VA_ARGS__), \
 	MACRO__(0x5693, ## __VA_ARGS__), \
 	MACRO__(0x5694, ## __VA_ARGS__), \
 	MACRO__(0x5695, ## __VA_ARGS__), \
-	MACRO__(0x56A5, ## __VA_ARGS__), \
-	MACRO__(0x56A6, ## __VA_ARGS__), \
-	MACRO__(0x56B0, ## __VA_ARGS__), \
-	MACRO__(0x56B1, ## __VA_ARGS__), \
 	MACRO__(0x56BA, ## __VA_ARGS__), \
 	MACRO__(0x56BB, ## __VA_ARGS__), \
 	MACRO__(0x56BC, ## __VA_ARGS__), \
 	MACRO__(0x56BD, ## __VA_ARGS__)
 
-#define INTEL_DG2_G12_IDS(MACRO__, ...) \
-	MACRO__(0x5696, ## __VA_ARGS__), \
-	MACRO__(0x5697, ## __VA_ARGS__), \
+#define INTEL_DG2_G12_WA_IDS(MACRO__, ...) \
 	MACRO__(0x56A3, ## __VA_ARGS__), \
 	MACRO__(0x56A4, ## __VA_ARGS__), \
 	MACRO__(0x56B2, ## __VA_ARGS__), \
 	MACRO__(0x56B3, ## __VA_ARGS__)
 
+#define INTEL_DG2_G12_IDS(MACRO__, ...) \
+	INTEL_DG2_G11_WA_IDS(MACRO__, ## __VA_ARGS__), \
+	MACRO__(0x5696, ## __VA_ARGS__), \
+	MACRO__(0x5697, ## __VA_ARGS__)
+
+#define INTEL_DG2_WA_IDS(MACRO__, ...) \
+	INTEL_DG2_G10_WA_IDS(MACRO__, ## __VA_ARGS__), \
+	INTEL_DG2_G11_WA_IDS(MACRO__, ## __VA_ARGS__), \
+	INTEL_DG2_G12_WA_IDS(MACRO__, ## __VA_ARGS__)
+
 #define INTEL_DG2_IDS(MACRO__, ...) \
 	INTEL_DG2_G10_IDS(MACRO__, ## __VA_ARGS__), \
 	INTEL_DG2_G11_IDS(MACRO__, ## __VA_ARGS__), \