diff mbox series

[16/16] drm/i915/dp: Add Check for Odd Pixel Requirement

Message ID 20241021123414.3993899-17-ankit.k.nautiyal@intel.com (mailing list archive)
State New, archived
Headers show
Series Add support for 3 VDSC engines 12 slices | expand

Commit Message

Nautiyal, Ankit K Oct. 21, 2024, 12:34 p.m. UTC 
Check if Odd pixel is required during DSC compute config and update
the crtc_state to track the presence of odd pixels.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 433a629c2bae..44e7069c4d27 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2366,6 +2366,14 @@  static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
 	return 0;
 }
 
+static bool intel_dp_dsc_needs_odd_pixel(int hdisplay, int replicated_pixels, int num_pipes)
+{
+	if (!replicated_pixels || num_pipes == 1)
+		return false;
+
+	return ((hdisplay + replicated_pixels) / num_pipes) % 2;
+}
+
 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 				struct intel_crtc_state *pipe_config,
 				struct drm_connector_state *conn_state,
@@ -2452,6 +2460,10 @@  int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 						adjusted_mode->crtc_hdisplay,
 						pipe_config->dsc.slice_count,
 						pipe_config->output_format);
+	pipe_config->dsc.has_odd_pixel =
+		intel_dp_dsc_needs_odd_pixel(adjusted_mode->crtc_hdisplay,
+					     pipe_config->dsc.replicated_pixels,
+					     num_joined_pipes);
 
 	/*
 	 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate